2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #define RAMINIT_SYSINFO 1
27 #define FAM10_SCAN_PCI_BUS 0
28 #define FAM10_ALLOCATE_IO_RANGE 1
30 #define QRANK_DIMM_SUPPORT 1
32 #if CONFIG_LOGICAL_CPUS==1
33 #define SET_NB_CFG_54 1
36 #define FAM10_SET_FIDVID 1
37 #define FAM10_SET_FIDVID_CORE_RANGE 0
39 #define DBGP_DEFAULT 7
43 #include <device/pci_def.h>
44 #include <device/pci_ids.h>
46 #include <device/pnp_def.h>
47 #include <arch/romcc_io.h>
48 #include <cpu/x86/lapic.h>
49 #include "option_table.h"
50 #include "pc80/mc146818rtc_early.c"
51 #include "pc80/serial.c"
52 #include "arch/i386/lib/console.c"
53 #if CONFIG_USBDEBUG_DIRECT
54 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
55 #include "pc80/usbdebug_direct_serial.c"
57 #include "lib/ramtest.c"
59 #include <cpu/amd/model_10xxx_rev.h>
61 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
62 #include "northbridge/amd/amdfam10/raminit.h"
63 #include "northbridge/amd/amdfam10/amdfam10.h"
65 #include "cpu/x86/lapic/boot_cpu.c"
66 #include "northbridge/amd/amdfam10/reset_test.c"
67 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
69 #include "cpu/x86/bist.h"
71 #include "northbridge/amd/amdfam10/debug.c"
73 #include "cpu/amd/mtrr/amd_earlymtrr.c"
75 #include "northbridge/amd/amdfam10/setup_resource_map.c"
77 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
78 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
80 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
82 static void memreset_setup(void)
86 static void memreset(int controllers, const struct mem_controller *ctrl)
90 static inline void activate_spd_rom(const struct mem_controller *ctrl)
95 static inline int spd_read_byte(unsigned device, unsigned address)
97 return smbus_read_byte(device, address);
100 #include "northbridge/amd/amdfam10/amdfam10.h"
101 #include "northbridge/amd/amdht/ht_wrapper.c"
103 #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
104 #include "northbridge/amd/amdfam10/raminit_amdmct.c"
105 #include "northbridge/amd/amdfam10/amdfam10_pci.c"
107 #include "resourcemap.c"
109 #include "cpu/amd/quadcore/quadcore.c"
112 #define MCP55_USE_NIC 1
113 #define MCP55_USE_AZA 1
115 #define MCP55_PCI_E_X_0 1
117 #define MCP55_MB_SETUP \
118 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
119 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
120 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
121 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
122 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
123 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
125 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
126 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
128 #include "cpu/amd/car/copy_and_run.c"
130 #include "cpu/amd/car/post_cache_as_ram.c"
132 #include "cpu/amd/model_10xxx/init_cpus.c"
134 #include "cpu/amd/model_10xxx/fidvid.c"
136 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
137 #include "northbridge/amd/amdfam10/early_ht.c"
139 static void sio_setup(void)
145 byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
147 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
149 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
151 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
154 #include "spd_addr.h"
155 #include "cpu/amd/microcode/microcode.c"
156 #include "cpu/amd/model_10xxx/update_microcode.c"
158 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
160 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
168 if (!cpu_init_detectedx && boot_cpu()) {
169 /* Nothing special needs to be done to find bus 0 */
170 /* Allow the HT devices to be found */
172 set_bsp_node_CHtExtNodeCfgEn();
173 enumerate_ht_chain();
177 /* Setup the mcp55 */
184 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
189 pnp_enter_ext_func_mode(SERIAL_DEV);
190 /* We have 24MHz input. */
191 reg = pnp_read_config(SERIAL_DEV, 0x24);
192 pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
193 pnp_exit_ext_func_mode(SERIAL_DEV);
195 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
198 printk(BIOS_DEBUG, "\n");
200 /* Halt if there was a built in self test failure */
201 report_bist_failure(bist);
203 #if CONFIG_USBDEBUG_DIRECT
204 mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
205 early_usbdebug_direct_init();
209 printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
210 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
211 printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
212 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
214 /* Setup sysinfo defaults */
215 set_sysinfo_in_ram(0);
217 update_microcode(val);
223 amd_ht_init(sysinfo);
226 /* Setup nodes PCI space and start core 0 AP init. */
227 finalize_node_setup(sysinfo);
228 printk(BIOS_DEBUG, "finalize_node_setup done\n");
230 /* Setup any mainboard PCI settings etc. */
231 printk(BIOS_DEBUG, "setup_mb_resource_map begin\n");
232 setup_mb_resource_map();
233 printk(BIOS_DEBUG, "setup_mb_resource_map end\n");
236 /* wait for all the APs core0 started by finalize_node_setup. */
237 /* FIXME: A bunch of cores are going to start output to serial at once.
238 * It would be nice to fixup prink spinlocks for ROM XIP mode.
239 * I think it could be done by putting the spinlock flag in the cache
240 * of the BSP located right after sysinfo.
242 wait_all_core0_started();
244 #if CONFIG_LOGICAL_CPUS==1
245 /* Core0 on each node is configured. Now setup any additional cores. */
246 printk(BIOS_DEBUG, "start_other_cores()\n");
249 printk(BIOS_DEBUG, "wait_all_other_cores_started()\n");
250 wait_all_other_cores_started(bsp_apicid);
255 #if FAM10_SET_FIDVID == 1
256 msr = rdmsr(0xc0010071);
257 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
259 /* FIXME: The sb fid change may survive the warm reset and only
260 * need to be done once.*/
261 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
265 if (!warm_reset_detect(0)) { // BSP is node 0
266 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
268 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
273 /* show final fid and vid */
274 msr=rdmsr(0xc0010071);
275 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
278 wants_reset = mcp55_early_setup_x();
280 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
281 if (!warm_reset_detect(0)) {
282 print_info("...WARM RESET...\n\n\n");
284 die("After soft_reset_x - shouldn't see this message!!!\n");
288 printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
292 /* It's the time to set ctrl in sysinfo now; */
293 printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
294 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
297 printk(BIOS_DEBUG, "enable_smbus()\n");
304 printk(BIOS_DEBUG, "raminit_amdmct()\n");
305 raminit_amdmct(sysinfo);
308 printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
309 post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
310 post_code(0x43); // Should never see this post code.