src/mainboard/msi/ms9282/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * Copyright (C) 2006 MSI
   8  * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #define ASSEMBLY 1
  26
  27
  28 #define RAMINIT_SYSINFO 1
  29 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
  30
  31 #define SET_NB_CFG_54 1
  32
  33 //used by raminit
  34 #define QRANK_DIMM_SUPPORT 1
  35
  36 //used by init_cpus and fidvid
  37 #define K8_SET_FIDVID 1
  38 //if we want to wait for core1 done before DQS training, set it to 0
  39 #define K8_SET_FIDVID_CORE0_ONLY 1
  40
  41 #include <stdint.h>
  42 #include <string.h>
  43 #include <device/pci_def.h>
  44 #include <arch/io.h>
  45 #include <device/pnp_def.h>
  46 #include <arch/romcc_io.h>
  47 #include <cpu/x86/lapic.h>
  48 #include "option_table.h"
  49 #include "pc80/mc146818rtc_early.c"
  50 #include "pc80/serial.c"
  51 #include "arch/i386/lib/console.c"
  52
  53 #include <cpu/amd/model_fxx_rev.h>
  54 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  55 #include "northbridge/amd/amdk8/raminit.h"
  56 #include "cpu/amd/model_fxx/apic_timer.c"
  57 #include "lib/delay.c"
  58
  59 #include "cpu/x86/lapic/boot_cpu.c"
  60 #include "northbridge/amd/amdk8/reset_test.c"
  61 #include "northbridge/amd/amdk8/debug.c"
  62 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  63
  64 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  65 #include "cpu/x86/bist.h"
  66
  67 #include "northbridge/amd/amdk8/setup_resource_map.c"
  68
  69 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  70 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
  71
  72 #include <device/pci_ids.h>
  73 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  74 static void memreset_setup(void)
  75 {
  76 }
  77
  78 static void memreset(int controllers, const struct mem_controller *ctrl)
  79 {
  80 }
  81
  82 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  83 {
  84 #define SMBUS_SWITCH1 0x70
  85 #define SMBUS_SWITCH2 0x72
  86         unsigned device=(ctrl->channel0[0])>>8;
  87         smbus_send_byte(SMBUS_SWITCH1, device);
  88        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  89 }
  90
  91 #if 0
  92 static inline void change_i2c_mux(unsigned device)
  93 {
  94 #define SMBUS_SWITCH1 0x70
  95 #define SMBUS_SWITHC2 0x72
  96         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  97        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  98 }
  99 #endif
 100
 101 static inline int spd_read_byte(unsigned device, unsigned address)
 102 {
 103        return smbus_read_byte(device, address);
 104 }
 105
 106 //#define K8_4RANK_DIMM_SUPPORT 1
 107
 108 #include "northbridge/amd/amdk8/amdk8_f.h"
 109 #include "northbridge/amd/amdk8/raminit_f.c"
 110 #include "northbridge/amd/amdk8/coherent_ht.c"
 111 #include "northbridge/amd/amdk8/incoherent_ht.c"
 112 #include "lib/generic_sdram.c"
 113
 114  /* msi does not want the default */
 115 #include "resourcemap.c"
 116 #include "cpu/amd/dualcore/dualcore.c"
 117
 118 #define MCP55_NUM 1
 119 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 120 //set GPIO to input mode
 121 #define MCP55_MB_SETUP \
 122                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
 123                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
 124                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
 125                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 126
 127 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 128
 129 #include "cpu/amd/car/copy_and_run.c"
 130
 131 #include "cpu/amd/car/post_cache_as_ram.c"
 132
 133 #include "cpu/amd/model_fxx/init_cpus.c"
 134 #include "cpu/amd/model_fxx/fidvid.c"
 135
 136 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 137 #include "northbridge/amd/amdk8/early_ht.c"
 138
 139
 140 static void sio_setup(void)
 141 {
 142
 143         unsigned value;
 144         uint32_t dword;
 145         uint8_t byte;
 146
 147         byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 148         byte |= 0x20;
 149         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 150
 151         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 152         dword |= (1<<0);
 153         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 154
 155
 156 }
 157
 158 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
 159 #define RC0 (2<<8)
 160 #define RC1 (1<<8)
 161
 162 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 163 {
 164        static const uint16_t spd_addr [] = {
 165                        RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
 166                        RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
 167 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 168                        RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
 169                        RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
 170 #endif
 171        };
 172
 173        unsigned bsp_apicid = 0;
 174         int needs_reset;
 175        struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 176        char *p ;
 177
 178         if (!cpu_init_detectedx && boot_cpu()) {
 179                 /* Nothing special needs to be done to find bus 0 */
 180                 /* Allow the HT devices to be found */
 181
 182                 enumerate_ht_chain();
 183
 184                 sio_setup();
 185
 186                 /* Setup the mcp55 */
 187                 mcp55_enable_rom();
 188         }
 189
 190         if (bist == 0) {
 191                //init_cpus(cpu_init_detectedx);
 192                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 193         }
 194
 195        w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 196         uart_init();
 197         console_init();
 198
 199        /* Halt if there was a built in self test failure */
 200        report_bist_failure(bist);
 201
 202         setup_ms9282_resource_map();
 203
 204        setup_coherent_ht_domain();
 205
 206         wait_all_core0_started();
 207
 208 #if CONFIG_LOGICAL_CPUS==1
 209         // It is said that we should start core1 after all core0 launched
 210         start_other_cores();
 211         //wait_all_other_cores_started(bsp_apicid);
 212 #endif
 213         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 214
 215        needs_reset = optimize_link_coherent_ht();
 216
 217        needs_reset |= optimize_link_incoherent_ht(sysinfo);
 218
 219         needs_reset |= mcp55_early_setup_x();
 220
 221                if (needs_reset) {
 222                        print_info("ht reset -\r\n");
 223                        soft_reset();
 224                }
 225
 226         //It's the time to set ctrl now;
 227         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 228
 229        enable_smbus();
 230
 231 #if 0
 232         int i;
 233         for(i=4;i<8;i++) {
 234                 change_i2c_mux(i);
 235                 dump_smbus_registers();
 236         }
 237 #endif
 238
 239        memreset_setup();
 240
 241        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 242
 243        post_cache_as_ram();
 244
 245 }