src/mainboard/msi/ms9282/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * Copyright (C) 2006 MSI
   8  * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #define RAMINIT_SYSINFO 1
  26 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
  27
  28 #define SET_NB_CFG_54 1
  29
  30 //used by raminit
  31 #define QRANK_DIMM_SUPPORT 1
  32
  33 //used by init_cpus and fidvid
  34 #define SET_FIDVID 1
  35 //if we want to wait for core1 done before DQS training, set it to 0
  36 #define SET_FIDVID_CORE0_ONLY 1
  37
  38 #include <stdint.h>
  39 #include <string.h>
  40 #include <device/pci_def.h>
  41 #include <arch/io.h>
  42 #include <device/pnp_def.h>
  43 #include <arch/romcc_io.h>
  44 #include <cpu/x86/lapic.h>
  45 #include <pc80/mc146818rtc.h>
  46 #include <console/console.h>
  47
  48 #include <cpu/amd/model_fxx_rev.h>
  49 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
  50 #include "northbridge/amd/amdk8/raminit.h"
  51 #include "cpu/amd/model_fxx/apic_timer.c"
  52 #include "lib/delay.c"
  53
  54 #include "cpu/x86/lapic/boot_cpu.c"
  55 #include "northbridge/amd/amdk8/reset_test.c"
  56 #include "northbridge/amd/amdk8/debug.c"
  57 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
  58
  59 #include "cpu/x86/mtrr/earlymtrr.c"
  60 #include "cpu/x86/bist.h"
  61
  62 #include "northbridge/amd/amdk8/setup_resource_map.c"
  63
  64 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
  65 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
  66
  67 #include <device/pci_ids.h>
  68 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
  69
  70 static void memreset(int controllers, const struct mem_controller *ctrl)
  71 {
  72 }
  73
  74 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  75 {
  76 #define SMBUS_SWITCH1 0x70
  77 #define SMBUS_SWITCH2 0x72
  78         unsigned device=(ctrl->channel0[0])>>8;
  79         smbus_send_byte(SMBUS_SWITCH1, device);
  80        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  81 }
  82
  83 #if 0
  84 static inline void change_i2c_mux(unsigned device)
  85 {
  86 #define SMBUS_SWITCH1 0x70
  87 #define SMBUS_SWITHC2 0x72
  88         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  89        smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
  90 }
  91 #endif
  92
  93 static inline int spd_read_byte(unsigned device, unsigned address)
  94 {
  95        return smbus_read_byte(device, address);
  96 }
  97
  98 //#define K8_4RANK_DIMM_SUPPORT 1
  99
 100 #include "northbridge/amd/amdk8/amdk8_f.h"
 101 #include "northbridge/amd/amdk8/incoherent_ht.c"
 102 #include "northbridge/amd/amdk8/coherent_ht.c"
 103 #include "northbridge/amd/amdk8/raminit_f.c"
 104 #include "lib/generic_sdram.c"
 105
 106  /* msi does not want the default */
 107 #include "resourcemap.c"
 108 #include "cpu/amd/dualcore/dualcore.c"
 109
 110 #define MCP55_NUM 1
 111 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
 112 //set GPIO to input mode
 113 #define MCP55_MB_SETUP \
 114                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
 115                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
 116                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
 117                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
 118
 119 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
 120
 121 #include "cpu/amd/car/post_cache_as_ram.c"
 122
 123 #include "cpu/amd/model_fxx/init_cpus.c"
 124 #include "cpu/amd/model_fxx/fidvid.c"
 125
 126 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 127 #include "northbridge/amd/amdk8/early_ht.c"
 128
 129 static void sio_setup(void)
 130 {
 131         uint32_t dword;
 132         uint8_t byte;
 133
 134         byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
 135         byte |= 0x20;
 136         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
 137
 138         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
 139         dword |= (1<<0);
 140         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
 141 }
 142
 143 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
 144 #define RC0 (2<<8)
 145 #define RC1 (1<<8)
 146
 147 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 148 {
 149         static const uint16_t spd_addr[] = {
 150                 // Node 0
 151                 RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
 152                 RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
 153                 // node 1
 154                 RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
 155                 RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
 156         };
 157
 158         unsigned bsp_apicid = 0;
 159         int needs_reset;
 160         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 161                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 162
 163         if (!cpu_init_detectedx && boot_cpu()) {
 164                 /* Nothing special needs to be done to find bus 0 */
 165                 /* Allow the HT devices to be found */
 166
 167                 enumerate_ht_chain();
 168
 169                 sio_setup();
 170
 171                 /* Setup the mcp55 */
 172                 mcp55_enable_rom();
 173         }
 174
 175         if (bist == 0) {
 176                //init_cpus(cpu_init_detectedx);
 177                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 178         }
 179
 180         w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 181         uart_init();
 182         console_init();
 183
 184         /* Halt if there was a built in self test failure */
 185         report_bist_failure(bist);
 186
 187         setup_ms9282_resource_map();
 188
 189         setup_coherent_ht_domain();
 190
 191         wait_all_core0_started();
 192
 193 #if CONFIG_LOGICAL_CPUS==1
 194         // It is said that we should start core1 after all core0 launched
 195         start_other_cores();
 196         //wait_all_other_cores_started(bsp_apicid);
 197 #endif
 198         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 199
 200         init_timer(); /* Need to use TMICT to synconize FID/VID. */
 201
 202         needs_reset = optimize_link_coherent_ht();
 203         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 204         needs_reset |= mcp55_early_setup_x();
 205
 206         if (needs_reset) {
 207                 print_info("ht reset -\n");
 208                 soft_reset();
 209         }
 210
 211         //It's the time to set ctrl now;
 212         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 213
 214        enable_smbus();
 215
 216 #if 0
 217         int i;
 218         for(i=4;i<8;i++) {
 219                 change_i2c_mux(i);
 220                 dump_smbus_registers();
 221         }
 222 #endif
 223
 224        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 225
 226        post_cache_as_ram();
 227 }
 228