2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 AMD
5 * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 * Copyright (C) 2006 MSI
8 * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define RAMINIT_SYSINFO 1
29 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
31 #define SET_NB_CFG_54 1
34 #define QRANK_DIMM_SUPPORT 1
36 //used by init_cpus and fidvid
37 #define K8_SET_FIDVID 1
38 //if we want to wait for core1 done before DQS training, set it to 0
39 #define K8_SET_FIDVID_CORE0_ONLY 1
45 #include <device/pci_def.h>
47 #include <device/pnp_def.h>
48 #include <arch/romcc_io.h>
49 #include <cpu/x86/lapic.h>
50 #include "option_table.h"
51 #include "pc80/mc146818rtc_early.c"
52 #include "pc80/serial.c"
53 #include "arch/i386/lib/console.c"
55 #include <cpu/amd/model_fxx_rev.h>
56 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
57 #include "northbridge/amd/amdk8/raminit.h"
58 #include "cpu/amd/model_fxx/apic_timer.c"
59 #include "lib/delay.c"
61 #include "cpu/x86/lapic/boot_cpu.c"
62 #include "northbridge/amd/amdk8/reset_test.c"
63 #include "northbridge/amd/amdk8/debug.c"
64 #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
66 #include "cpu/amd/mtrr/amd_earlymtrr.c"
67 #include "cpu/x86/bist.h"
69 #include "northbridge/amd/amdk8/setup_resource_map.c"
71 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
72 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)
74 #include <device/pci_ids.h>
75 #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
76 static void memreset_setup(void)
80 static void memreset(int controllers, const struct mem_controller *ctrl)
84 static inline void activate_spd_rom(const struct mem_controller *ctrl)
86 #define SMBUS_SWITCH1 0x70
87 #define SMBUS_SWITCH2 0x72
88 unsigned device=(ctrl->channel0[0])>>8;
89 smbus_send_byte(SMBUS_SWITCH1, device);
90 smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
94 static inline void change_i2c_mux(unsigned device)
96 #define SMBUS_SWITCH1 0x70
97 #define SMBUS_SWITHC2 0x72
98 smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
99 smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
103 static inline int spd_read_byte(unsigned device, unsigned address)
105 return smbus_read_byte(device, address);
108 //#define K8_4RANK_DIMM_SUPPORT 1
110 #include "northbridge/amd/amdk8/amdk8_f.h"
111 #include "northbridge/amd/amdk8/raminit_f.c"
112 #include "northbridge/amd/amdk8/coherent_ht.c"
113 #include "northbridge/amd/amdk8/incoherent_ht.c"
114 #include "sdram/generic_sdram.c"
116 /* msi does not want the default */
117 #include "resourcemap.c"
118 #include "cpu/amd/dualcore/dualcore.c"
121 #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
122 //set GPIO to input mode
123 #define MCP55_MB_SETUP \
124 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
125 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
126 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
127 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
129 #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
131 #include "cpu/amd/car/copy_and_run.c"
133 #include "cpu/amd/car/post_cache_as_ram.c"
135 #include "cpu/amd/model_fxx/init_cpus.c"
136 #include "cpu/amd/model_fxx/fidvid.c"
138 #if CONFIG_USE_FALLBACK_IMAGE == 1
140 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
141 #include "northbridge/amd/amdk8/early_ht.c"
144 static void sio_setup(void)
151 byte = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
153 pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
155 dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
157 pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
161 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
163 unsigned last_boot_normal_x = last_boot_normal();
165 /* Is this a cpu only reset? or Is this a secondary cpu? */
166 if ((cpu_init_detectedx) || (!boot_cpu())) {
167 if (last_boot_normal_x) {
174 /* Nothing special needs to be done to find bus 0 */
175 /* Allow the HT devices to be found */
177 enumerate_ht_chain();
181 /* Setup the mcp55 */
184 /* Is this a deliberate reset by the bios */
185 if (bios_reset_detected() && last_boot_normal_x) {
188 /* This is the primary cpu how should I boot? */
189 else if (do_normal_boot()) {
196 __asm__ volatile ("jmp __normal_image"
198 : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
206 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
208 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
211 #if CONFIG_USE_FALLBACK_IMAGE == 1
212 failover_process(bist, cpu_init_detectedx);
214 real_main(bist, cpu_init_detectedx);
218 //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
222 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
224 static const uint16_t spd_addr [] = {
225 RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
226 RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
227 #if CONFIG_MAX_PHYSICAL_CPUS > 1
228 RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
229 RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
233 unsigned bsp_apicid = 0;
235 struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
239 //init_cpus(cpu_init_detectedx);
240 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
243 w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
247 /* Halt if there was a built in self test failure */
248 report_bist_failure(bist);
250 setup_ms9282_resource_map();
252 setup_coherent_ht_domain();
254 wait_all_core0_started();
256 #if CONFIG_LOGICAL_CPUS==1
257 // It is said that we should start core1 after all core0 launched
259 //wait_all_other_cores_started(bsp_apicid);
261 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
263 needs_reset = optimize_link_coherent_ht();
265 needs_reset |= optimize_link_incoherent_ht(sysinfo);
267 needs_reset |= mcp55_early_setup_x();
270 print_info("ht reset -\r\n");
274 //It's the time to set ctrl now;
275 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
283 dump_smbus_registers();
289 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);