2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2006 MSI
8 ## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
10 ## This program is free software; you can redistribute it and/or modify
11 ## it under the terms of the GNU General Public License as published by
12 ## the Free Software Foundation; either version 2 of the License, or
13 ## (at your option) any later version.
15 ## This program is distributed in the hope that it will be useful,
16 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ## GNU General Public License for more details.
20 ## You should have received a copy of the GNU General Public License
21 ## along with this program; if not, write to the Free Software
22 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 uses CONFIG_HAVE_MP_TABLE
26 uses CONFIG_HAVE_PIRQ_TABLE
27 uses CONFIG_USE_FALLBACK_IMAGE
28 uses CONFIG_HAVE_FALLBACK_BOOT
29 uses CONFIG_HAVE_HARD_RESET
30 uses CONFIG_IRQ_SLOT_COUNT
31 uses CONFIG_HAVE_OPTION_TABLE
33 uses CONFIG_MAX_PHYSICAL_CPUS
34 uses CONFIG_LOGICAL_CPUS
37 uses CONFIG_FALLBACK_SIZE
39 uses CONFIG_ROM_SECTION_SIZE
40 uses CONFIG_ROM_IMAGE_SIZE
41 uses CONFIG_ROM_SECTION_SIZE
42 uses CONFIG_ROM_SECTION_OFFSET
43 uses CONFIG_ROM_PAYLOAD
44 uses CONFIG_ROM_PAYLOAD_START
45 uses CONFIG_PAYLOAD_SIZE
47 uses CONFIG_XIP_ROM_SIZE
48 uses CONFIG_XIP_ROM_BASE
49 uses CONFIG_STACK_SIZE
51 uses CONFIG_USE_OPTION_TABLE
52 uses CONFIG_LB_CKS_RANGE_START
53 uses CONFIG_LB_CKS_RANGE_END
54 uses CONFIG_LB_CKS_LOC
56 uses CONFIG_MAINBOARD_PART_NUMBER
57 uses CONFIG_MAINBOARD_VENDOR
58 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
59 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
60 uses COREBOOT_EXTRA_VERSION
63 uses CONFIG_CROSS_COMPILE
67 uses CONFIG_TTYS0_BAUD
68 uses CONFIG_TTYS0_BASE
70 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
71 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
72 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
73 uses CONFIG_CONSOLE_SERIAL8250
74 uses CONFIG_HAVE_INIT_TIMER
76 uses CONFIG_CONSOLE_VGA
77 uses CONFIG_PCI_ROM_RUN
78 #bx_b001- uses K8_HW_MEM_HOLE_SIZEK
79 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
81 uses CONFIG_USE_DCACHE_RAM
82 uses CONFIG_DCACHE_RAM_BASE
83 uses CONFIG_DCACHE_RAM_SIZE
84 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
87 uses CONFIG_ENABLE_APIC_EXT_ID
88 uses CONFIG_APIC_ID_OFFSET
89 uses CONFIG_LIFT_BSP_APIC_ID
91 uses CONFIG_HT_CHAIN_UNITID_BASE
92 uses CONFIG_HT_CHAIN_END_UNITID_BASE
93 #bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
94 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
96 uses CONFIG_SB_HT_CHAIN_ON_BUS0
99 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
100 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
101 uses CONFIG_PRECOMPRESSED_PAYLOAD
102 uses CONFIG_USE_PRINTK_IN_CAR
104 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
106 default CONFIG_ROM_SIZE=524288
109 #bx- default CONFIG_ROM_SIZE=1048576
112 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
114 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
121 ## Build code for the fallback boot
123 default CONFIG_HAVE_FALLBACK_BOOT=1
126 ## Build code to reset the motherboard from coreboot
128 default CONFIG_HAVE_HARD_RESET=1
131 ## Build code to export a programmable irq routing table
133 default CONFIG_HAVE_PIRQ_TABLE=1
134 default CONFIG_IRQ_SLOT_COUNT=11
137 ## Build code to export an x86 MP table
138 ## Useful for specifying IRQ routing values
140 default CONFIG_HAVE_MP_TABLE=1
143 ## Build code to export a CMOS option table
145 default CONFIG_HAVE_OPTION_TABLE=1
148 ## Move the default coreboot cmos range off of AMD RTC registers
150 default CONFIG_LB_CKS_RANGE_START=49
151 default CONFIG_LB_CKS_RANGE_END=122
152 default CONFIG_LB_CKS_LOC=123
155 ## Build code for SMP support
156 ## Only worry about 2 micro processors
159 default CONFIG_MAX_CPUS=4
160 default CONFIG_MAX_PHYSICAL_CPUS=2
161 default CONFIG_LOGICAL_CPUS=1
164 #bx_b001- default K8_HW_MEM_HOLE_SIZEK=0x100000
166 #Opteron K8 1G HT Support
167 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
169 ##HT Unit ID offset, default is 1, the typical one
170 default CONFIG_HT_CHAIN_UNITID_BASE=0x0
172 ##real SB Unit ID, default is 0x20, mean dont touch it at last
173 #default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
175 #make the SB HT chain on bus 0, default is not (0)
176 #bx_b001- default K8_SB_HT_CHAIN_ON_BUS0=2
178 ##bx_b005+ make the SB HT chain on bus 0
179 default CONFIG_SB_HT_CHAIN_ON_BUS0=1
181 ##only offset for SB chain?, default is yes(1)
182 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
185 default CONFIG_CONSOLE_VGA=1
186 default CONFIG_PCI_ROM_RUN=1
189 ## enable CACHE_AS_RAM specifics
191 default CONFIG_USE_DCACHE_RAM=1
192 default CONFIG_DCACHE_RAM_BASE=0xcc000
193 default CONFIG_DCACHE_RAM_SIZE=0x4000
194 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
195 default CONFIG_USE_INIT=0
197 default CONFIG_ENABLE_APIC_EXT_ID=1
198 default CONFIG_APIC_ID_OFFSET=0x10
199 default CONFIG_LIFT_BSP_APIC_ID=0
202 ## Build code to setup a generic IOAPIC
204 default CONFIG_IOAPIC=1
207 ## Clean up the motherboard id strings
209 default CONFIG_MAINBOARD_PART_NUMBER="ms9282"
210 default CONFIG_MAINBOARD_VENDOR="MSI"
211 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1462
212 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x9282
215 ### coreboot layout values
218 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
219 default CONFIG_ROM_IMAGE_SIZE = 65536
222 ## Use a small 8K stack
224 default CONFIG_STACK_SIZE=0x2000
227 ## Use a small 16K heap
229 default CONFIG_HEAP_SIZE=0x4000
232 ## Only use the option table in a normal image
234 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
237 ## Coreboot C code runs at this location in RAM
239 default CONFIG_RAMBASE=0x00004000
242 ## Load the payload from the ROM
244 default CONFIG_ROM_PAYLOAD = 1
247 ### Defaults of options that you may want to override in the target config file
251 ## The default compiler
253 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
257 ## Disable the gdb stub by default
259 default CONFIG_GDB_STUB=0
262 ## The Serial Console
264 default CONFIG_USE_PRINTK_IN_CAR=1
266 # To Enable the Serial Console
267 default CONFIG_CONSOLE_SERIAL8250=1
269 ## Select the serial console baud rate
270 default CONFIG_TTYS0_BAUD=115200
271 #default CONFIG_TTYS0_BAUD=57600
272 #default CONFIG_TTYS0_BAUD=38400
273 #default CONFIG_TTYS0_BAUD=19200
274 #default CONFIG_TTYS0_BAUD=9600
275 #default CONFIG_TTYS0_BAUD=4800
276 #default CONFIG_TTYS0_BAUD=2400
277 #default CONFIG_TTYS0_BAUD=1200
279 # Select the serial console base port
280 default CONFIG_TTYS0_BASE=0x3f8
282 # Select the serial protocol
283 # This defaults to 8 data bits, 1 stop bit, and no parity
284 default CONFIG_TTYS0_LCS=0x3
287 ### Select the coreboot loglevel
289 ## EMERG 1 system is unusable
290 ## ALERT 2 action must be taken immediately
291 ## CRIT 3 critical conditions
292 ## ERR 4 error conditions
293 ## WARNING 5 warning conditions
294 ## NOTICE 6 normal but significant condition
295 ## INFO 7 informational
296 ## CONFIG_DEBUG 8 debug-level messages
297 ## SPEW 9 Way too many details
299 ## Request this level of debugging output
300 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
301 ## At a maximum only compile in this level of debugging
302 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
305 ## Select power on after power fail setting
306 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"