2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2006 MSI
8 ## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
10 ## This program is free software; you can redistribute it and/or modify
11 ## it under the terms of the GNU General Public License as published by
12 ## the Free Software Foundation; either version 2 of the License, or
13 ## (at your option) any later version.
15 ## This program is distributed in the hope that it will be useful,
16 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ## GNU General Public License for more details.
20 ## You should have received a copy of the GNU General Public License
21 ## along with this program; if not, write to the Free Software
22 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 ## Compute the location and size of where this firmware image
27 ## (coreboot plus bootloader) will live in the boot rom chip.
30 default ROM_SECTION_SIZE = FALLBACK_SIZE
31 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
33 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
34 default ROM_SECTION_OFFSET = 0
38 ## Compute the start location and size size of
39 ## The coreboot bootloader.
41 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
42 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
43 default CONFIG_ROM_PAYLOAD = 1
46 ## Compute where this copy of coreboot will start in the boot rom
48 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
51 ## Compute a range of ROM that can cached to speed up coreboot,
54 ## XIP_ROM_SIZE must be a power of 2.
55 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
57 default XIP_ROM_SIZE=65536
58 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
64 ## Build the objects we have code for in this directory.
69 #dir /drivers/ati/ragexl
70 #needed by irq_tables and mptable and acpi_tables
74 if HAVE_MP_TABLE object mptable.o end
75 if HAVE_PIRQ_TABLE object irq_tables.o end
81 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
82 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
88 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
89 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
90 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
91 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
97 ## Build our 16 bit and 32 bit coreboot entry code
100 mainboardinit cpu/x86/16bit/entry16.inc
101 ldscript /cpu/x86/16bit/entry16.lds
104 mainboardinit cpu/x86/32bit/entry32.inc
107 ldscript /cpu/x86/32bit/entry32.lds
111 ldscript /cpu/amd/car/cache_as_ram.lds
115 ## Build our reset vector (This is where coreboot is entered)
117 if USE_FALLBACK_IMAGE
118 mainboardinit cpu/x86/16bit/reset16.inc
119 ldscript /cpu/x86/16bit/reset16.lds
121 mainboardinit cpu/x86/32bit/reset32.inc
122 ldscript /cpu/x86/32bit/reset32.lds
126 ## Include an id string (For safe flashing)
128 mainboardinit southbridge/nvidia/mcp55/id.inc
129 ldscript /southbridge/nvidia/mcp55/id.lds
132 ## ROMSTRAP table for MCP55
134 if USE_FALLBACK_IMAGE
135 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
136 ldscript /southbridge/nvidia/mcp55/romstrap.lds
140 ## Setup Cache-As-Ram
142 mainboardinit cpu/amd/car/cache_as_ram.inc
145 ### This is the early phase of coreboot startup
146 ### Things are delicate and we test to see if we should
147 ### failover to another image.
149 if USE_FALLBACK_IMAGE
150 ldscript /arch/i386/lib/failover.lds
154 ### O.k. We aren't just an intermediary anymore!
163 mainboardinit ./auto.inc
167 ## Include the secondary Configuration files
172 # sample config for msi/ms9282
173 chip northbridge/amd/amdk8/root_complex
174 device apic_cluster 0 on
175 chip cpu/amd/socket_F
180 device pci_domain 0 on
181 chip northbridge/amd/amdk8 #mc0
182 device pci 18.0 on # northbridge
183 # devices on link 0, link 0 == LDT 0
184 chip southbridge/nvidia/mcp55
185 device pci 0.0 on end # HT
186 device pci 1.0 on # LPC
187 chip superio/winbond/w83627ehg
188 device pnp 2e.0 on # Floppy
193 device pnp 2e.1 off # Parallel Port
197 device pnp 2e.2 on # Com1
201 device pnp 2e.3 off # Com2
205 device pnp 2e.5 on # Keyboard
211 device pnp 2e.6 off # SERIAL_FALSH
214 device pnp 2e.7 off # GAME_MIDI_GIPO1
219 device pnp 2e.8 off end # WDTO_PLED
220 device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5
221 device pnp 2e.a off end # ACPI
222 device pnp 2e.b on # HW Monitor
228 device pci 1.1 on # SM 0
229 chip drivers/i2c/i2cmux2 # pca9554 smbus mux
230 device i2c 70 on #0 pca9554 1
231 chip drivers/generic/generic #dimm 0-0-0
234 chip drivers/generic/generic #dimm 0-0-1
237 chip drivers/generic/generic #dimm 0-1-0
240 chip drivers/generic/generic #dimm 0-1-1
243 chip drivers/generic/generic #dimm 0-0-0
246 chip drivers/generic/generic #dimm 0-0-1
249 chip drivers/generic/generic #dimm 0-1-0
252 chip drivers/generic/generic #dimm 0-1-1
256 device i2c 70 on #0 pca9554 2
257 chip drivers/generic/generic #dimm 0-0-0
260 chip drivers/generic/generic #dimm 0-0-1
263 chip drivers/generic/generic #dimm 0-1-0
266 chip drivers/generic/generic #dimm 0-1-1
269 chip drivers/generic/generic #dimm 0-0-0
272 chip drivers/generic/generic #dimm 0-0-1
275 chip drivers/generic/generic #dimm 0-1-0
278 chip drivers/generic/generic #dimm 0-1-1
284 device pci 1.1 on # SM 1
285 chip drivers/i2c/i2cmux2 # pca9554 smbus mux
286 device i2c 72 on #pca9554 channle1
287 chip drivers/i2c/adm1027 #HWM ADT7476 1
291 device i2c 72 on #pca9545 channel 2
292 chip drivers/i2c/adm1027 #HWM ADT7463
296 device i2c 72 on end #pca9545 channel 3
297 device i2c 72 on #pca9545 channel 4
298 chip drivers/i2c/adm1027 #HWM ADT7476 2
305 device pci 2.0 on end # USB 1.1
306 device pci 2.1 on end # USB 2
307 device pci 4.0 on end # IDE
308 device pci 5.0 on end # SATA 0
309 device pci 5.1 on end # SATA 1
310 device pci 5.2 on end # SATA 2
311 device pci 6.0 on #P2P
312 chip drivers/pci/onboard
313 device pci 4.0 on end
314 register "rom_address" = "0xfff80000"
317 device pci 7.0 on end # reserve
318 device pci 8.0 on end # MAC0
319 device pci 9.0 on end # MAC1
322 chip drivers/pci/onboard
323 device pci 4.0 on end #pci_E lan1
324 device pci 4.1 on end #pci_E lan2
328 device pci b.0 on end # PCI E 0x374
329 device pci c.0 on end
330 device pci d.0 on #SAS
331 chip drivers/pci/onboard
332 device pci 0.0 on end
335 device pci e.0 on end # PCI E 0 0x375
336 device pci f.0 on end #PCI E 0x377 pci_E slot
337 register "ide0_enable" = "1"
338 register "ide1_enable" = "1"
339 register "sata0_enable" = "1"
340 register "sata1_enable" = "1"
342 end # device pci 18.0
343 device pci 18.0 on end # Link 1
344 device pci 18.0 on end
345 device pci 18.1 on end
346 device pci 18.2 on end
347 device pci 18.3 on end
352 # chip drivers/generic/debug
353 # device pnp 0.0 off end
354 # device pnp 0.1 off end
355 # device pnp 0.2 off end
356 # device pnp 0.3 off end
357 # device pnp 0.4 off end
358 # device pnp 0.5 on end