2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2006 MSI
8 ## Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
10 ## This program is free software; you can redistribute it and/or modify
11 ## it under the terms of the GNU General Public License as published by
12 ## the Free Software Foundation; either version 2 of the License, or
13 ## (at your option) any later version.
15 ## This program is distributed in the hope that it will be useful,
16 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ## GNU General Public License for more details.
20 ## You should have received a copy of the GNU General Public License
21 ## along with this program; if not, write to the Free Software
22 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 include /config/nofailovercalculation.lb
26 default CONFIG_ROM_PAYLOAD = 1
32 ## Build the objects we have code for in this directory.
37 #dir /drivers/ati/ragexl
38 #needed by irq_tables and mptable and acpi_tables
42 if HAVE_MP_TABLE object mptable.o end
43 if HAVE_PIRQ_TABLE object irq_tables.o end
49 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
50 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
56 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
57 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
58 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
59 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
65 ## Build our 16 bit and 32 bit coreboot entry code
68 mainboardinit cpu/x86/16bit/entry16.inc
69 ldscript /cpu/x86/16bit/entry16.lds
72 mainboardinit cpu/x86/32bit/entry32.inc
75 ldscript /cpu/x86/32bit/entry32.lds
79 ldscript /cpu/amd/car/cache_as_ram.lds
83 ## Build our reset vector (This is where coreboot is entered)
86 mainboardinit cpu/x86/16bit/reset16.inc
87 ldscript /cpu/x86/16bit/reset16.lds
89 mainboardinit cpu/x86/32bit/reset32.inc
90 ldscript /cpu/x86/32bit/reset32.lds
94 ## Include an id string (For safe flashing)
96 mainboardinit southbridge/nvidia/mcp55/id.inc
97 ldscript /southbridge/nvidia/mcp55/id.lds
100 ## ROMSTRAP table for MCP55
102 if USE_FALLBACK_IMAGE
103 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
104 ldscript /southbridge/nvidia/mcp55/romstrap.lds
108 ## Setup Cache-As-Ram
110 mainboardinit cpu/amd/car/cache_as_ram.inc
113 ### This is the early phase of coreboot startup
114 ### Things are delicate and we test to see if we should
115 ### failover to another image.
117 if USE_FALLBACK_IMAGE
118 ldscript /arch/i386/lib/failover.lds
122 ### O.k. We aren't just an intermediary anymore!
131 mainboardinit ./auto.inc
135 ## Include the secondary Configuration files
140 # sample config for msi/ms9282
141 chip northbridge/amd/amdk8/root_complex
142 device apic_cluster 0 on
143 chip cpu/amd/socket_F
148 device pci_domain 0 on
149 chip northbridge/amd/amdk8 #mc0
150 device pci 18.0 on # northbridge
151 # devices on link 0, link 0 == LDT 0
152 chip southbridge/nvidia/mcp55
153 device pci 0.0 on end # HT
154 device pci 1.0 on # LPC
155 chip superio/winbond/w83627ehg
156 device pnp 2e.0 on # Floppy
161 device pnp 2e.1 off # Parallel Port
165 device pnp 2e.2 on # Com1
169 device pnp 2e.3 off # Com2
173 device pnp 2e.5 on # Keyboard
179 device pnp 2e.6 off # SERIAL_FALSH
182 device pnp 2e.7 off # GAME_MIDI_GIPO1
187 device pnp 2e.8 off end # WDTO_PLED
188 device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5
189 device pnp 2e.a off end # ACPI
190 device pnp 2e.b on # HW Monitor
196 device pci 1.1 on # SM 0
197 chip drivers/i2c/i2cmux2 # pca9554 smbus mux
198 device i2c 70 on #0 pca9554 1
199 chip drivers/generic/generic #dimm 0-0-0
202 chip drivers/generic/generic #dimm 0-0-1
205 chip drivers/generic/generic #dimm 0-1-0
208 chip drivers/generic/generic #dimm 0-1-1
211 chip drivers/generic/generic #dimm 0-0-0
214 chip drivers/generic/generic #dimm 0-0-1
217 chip drivers/generic/generic #dimm 0-1-0
220 chip drivers/generic/generic #dimm 0-1-1
224 device i2c 70 on #0 pca9554 2
225 chip drivers/generic/generic #dimm 0-0-0
228 chip drivers/generic/generic #dimm 0-0-1
231 chip drivers/generic/generic #dimm 0-1-0
234 chip drivers/generic/generic #dimm 0-1-1
237 chip drivers/generic/generic #dimm 0-0-0
240 chip drivers/generic/generic #dimm 0-0-1
243 chip drivers/generic/generic #dimm 0-1-0
246 chip drivers/generic/generic #dimm 0-1-1
252 device pci 1.1 on # SM 1
253 chip drivers/i2c/i2cmux2 # pca9554 smbus mux
254 device i2c 72 on #pca9554 channle1
255 chip drivers/i2c/adm1027 #HWM ADT7476 1
259 device i2c 72 on #pca9545 channel 2
260 chip drivers/i2c/adm1027 #HWM ADT7463
264 device i2c 72 on end #pca9545 channel 3
265 device i2c 72 on #pca9545 channel 4
266 chip drivers/i2c/adm1027 #HWM ADT7476 2
273 device pci 2.0 on end # USB 1.1
274 device pci 2.1 on end # USB 2
275 device pci 4.0 on end # IDE
276 device pci 5.0 on end # SATA 0
277 device pci 5.1 on end # SATA 1
278 device pci 5.2 on end # SATA 2
279 device pci 6.0 on #P2P
280 chip drivers/pci/onboard
281 device pci 4.0 on end
282 register "rom_address" = "0xfff80000"
285 device pci 7.0 on end # reserve
286 device pci 8.0 on end # MAC0
287 device pci 9.0 on end # MAC1
290 chip drivers/pci/onboard
291 device pci 4.0 on end #pci_E lan1
292 device pci 4.1 on end #pci_E lan2
296 device pci b.0 on end # PCI E 0x374
297 device pci c.0 on end
298 device pci d.0 on #SAS
299 chip drivers/pci/onboard
300 device pci 0.0 on end
303 device pci e.0 on end # PCI E 0 0x375
304 device pci f.0 on end #PCI E 0x377 pci_E slot
305 register "ide0_enable" = "1"
306 register "ide1_enable" = "1"
307 register "sata0_enable" = "1"
308 register "sata1_enable" = "1"
310 end # device pci 18.0
311 device pci 18.0 on end # Link 1
312 device pci 18.0 on end
313 device pci 18.1 on end
314 device pci 18.2 on end
315 device pci 18.3 on end
320 # chip drivers/generic/debug
321 # device pnp 0.0 off end
322 # device pnp 0.1 off end
323 # device pnp 0.2 off end
324 # device pnp 0.3 off end
325 # device pnp 0.4 off end
326 # device pnp 0.5 on end