src/mainboard/msi/ms9185/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2006 MSI
   9  * Written by bxshi <bingxunshi@gmail.com> for MSI.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #define SET_NB_CFG_54 1
  27
  28 #include <stdint.h>
  29 #include <string.h>
  30 #include <device/pci_def.h>
  31 #include <device/pci_ids.h>
  32 #include <arch/io.h>
  33 #include <device/pnp_def.h>
  34 #include <arch/romcc_io.h>
  35 #include <cpu/x86/lapic.h>
  36 #include <pc80/mc146818rtc.h>
  37 #include <console/console.h>
  38
  39 #include <cpu/amd/model_fxx_rev.h>
  40 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
  41 #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
  42 #include "northbridge/amd/amdk8/raminit.h"
  43 #include "cpu/amd/model_fxx/apic_timer.c"
  44 #include "lib/delay.c"
  45 #include <reset.h>
  46
  47 #include "cpu/x86/lapic/boot_cpu.c"
  48 #include "northbridge/amd/amdk8/reset_test.c"
  49 #include "northbridge/amd/amdk8/debug.c"
  50 #include "superio/nsc/pc87417/pc87417_early_serial.c"
  51 #include "cpu/x86/mtrr/earlymtrr.c"
  52 #include "cpu/x86/bist.h"
  53
  54 #include "northbridge/amd/amdk8/setup_resource_map.c"
  55
  56 #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
  57 #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
  58 #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
  59
  60 static void memreset(int controllers, const struct mem_controller *ctrl)
  61 {
  62 }
  63
  64 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  65 {
  66 #define SMBUS_SWITCH1 0x70
  67 #define SMBUS_SWITCH2 0x72
  68         unsigned device = (ctrl->channel0[0]) >> 8;
  69         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  70         smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
  71 }
  72
  73 #if 0
  74 static inline void change_i2c_mux(unsigned device)
  75 {
  76 #define SMBUS_SWITCH1 0x70
  77 #define SMBUS_SWITCH2 0x72
  78         smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
  79         smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f );
  80 }
  81 #endif
  82
  83 static inline int spd_read_byte(unsigned device, unsigned address)
  84 {
  85         return smbus_read_byte(device, address);
  86 }
  87
  88 #include "northbridge/amd/amdk8/amdk8_f.h"
  89 #include "northbridge/amd/amdk8/incoherent_ht.c"
  90 #include "northbridge/amd/amdk8/coherent_ht.c"
  91 #include "northbridge/amd/amdk8/raminit_f.c"
  92 #include "lib/generic_sdram.c"
  93
  94  /* msi does not want the default */
  95 #include "resourcemap.c"
  96
  97 #include "cpu/amd/dualcore/dualcore.c"
  98
  99 #define RC0 (0x10<<8)
 100 #define RC1 (0x01<<8)
 101
 102 #define DIMM0 0x50
 103 #define DIMM1 0x51
 104 #define DIMM2 0x52
 105 #define DIMM3 0x53
 106 #define DIMM4 0x54
 107 #define DIMM5 0x55
 108 #define DIMM6 0x56
 109 #define DIMM7 0x57
 110
 111 #include "cpu/amd/car/post_cache_as_ram.c"
 112
 113 #include "cpu/amd/model_fxx/init_cpus.c"
 114
 115 #include "cpu/amd/model_fxx/fidvid.c"
 116
 117 #include "northbridge/amd/amdk8/early_ht.c"
 118
 119 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 120 {
 121        static const uint16_t spd_addr[] = {
 122                        //first node
 123                         RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6,
 124                         RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7,
 125                        //second node
 126                        RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
 127                        RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
 128        };
 129
 130         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
 131                 CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 132
 133         int needs_reset;
 134         unsigned bsp_apicid = 0;
 135
 136         if (!cpu_init_detectedx && boot_cpu()) {
 137                 /* Nothing special needs to be done to find bus 0 */
 138                 /* Allow the HT devices to be found */
 139
 140                 enumerate_ht_chain();
 141
 142                 bcm5785_enable_rom();
 143
 144                 bcm5785_enable_lpc();
 145
 146                 //enable RTC
 147                 pc87417_enable_dev(RTC_DEV);
 148         }
 149
 150         if (bist == 0) {
 151                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 152         }
 153
 154 //     post_code(0x32);
 155
 156        pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 157         uart_init();
 158         console_init();
 159
 160 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 161
 162        /* Halt if there was a built in self test failure */
 163        report_bist_failure(bist);
 164
 165         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 166
 167        setup_ms9185_resource_map();
 168 #if 0
 169         dump_pci_device(PCI_DEV(0, 0x18, 0));
 170        dump_pci_device(PCI_DEV(0, 0x19, 0));
 171 #endif
 172
 173        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 174
 175        setup_coherent_ht_domain();
 176
 177        wait_all_core0_started();
 178 #if CONFIG_LOGICAL_CPUS==1
 179         // It is said that we should start core1 after all core0 launched
 180        /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 181         * So here need to make sure last core0 is started, esp for two way system,
 182         * (there may be apic id conflicts in that case)
 183         */
 184         start_other_cores();
 185 //bx_a010-     wait_all_other_cores_started(bsp_apicid);
 186 #endif
 187
 188        /* it will set up chains and store link pair for optimization later */
 189         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 190
 191        bcm5785_early_setup();
 192
 193 #if 0
 194        //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time.
 195         needs_reset = optimize_link_coherent_ht();
 196         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 197 #endif
 198
 199 #if CONFIG_SET_FIDVID
 200
 201         {
 202                 msr_t msr;
 203                 msr=rdmsr(0xc0010042);
 204                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 205
 206         }
 207
 208        enable_fid_change();
 209
 210        enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 211
 212         init_fidvid_bsp(bsp_apicid);
 213
 214         // show final fid and vid
 215         {
 216                 msr_t msr;
 217                 msr=rdmsr(0xc0010042);
 218                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 219
 220         }
 221 #endif
 222
 223 #if 1
 224        needs_reset = optimize_link_coherent_ht();
 225        needs_reset |= optimize_link_incoherent_ht(sysinfo);
 226
 227         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 228         if (needs_reset) {
 229                 print_info("ht reset -\n");
 230                 soft_reset();
 231         }
 232 #endif
 233        allow_all_aps_stop(bsp_apicid);
 234
 235         //It's the time to set ctrl in sysinfo now;
 236        fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 237
 238        enable_smbus();
 239
 240 #if 0
 241        int i;
 242        for(i=0;i<2;i++) {
 243                activate_spd_rom(sysinfo->ctrl+i);
 244                dump_smbus_registers();
 245        }
 246 #endif
 247
 248 #if 0
 249        int i;
 250         for(i=1;i<256;i<<=1) {
 251                 change_i2c_mux(i);
 252                 dump_smbus_registers();
 253         }
 254 #endif
 255
 256        //do we need apci timer, tsc...., only debug need it for better output
 257         /* all ap stopped? */
 258 //        init_timer(); // Need to use TMICT to synconize FID/VID
 259
 260        sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 261
 262 #if 0
 263         print_pci_devices();
 264 #endif
 265
 266 #if 0
 267 //        dump_pci_devices();
 268         dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
 269        dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
 270 #endif
 271
 272        post_cache_as_ram();
 273
 274 }
 275