2 * This file is part of the coreboot project.
4 * Copyright (C) 2003 Stefan Reinauer <stepan@coresystems.de>
6 * Copyright (C) 2006 AMD
7 * Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
9 * Copyright (C) 2006 MSI
10 * Written by bxshi <bingxunshi@gmail.com> for MSI.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 * ms9185 needs a different resource map
32 static void setup_ms9185_resource_map(void)
34 static const unsigned int register_values[] = {
35 /* Careful set limit registers before base registers which contain the enables */
36 /* DRAM Limit i Registers
45 * [ 2: 0] Destination Node ID
55 * [10: 8] Interleave select
56 * specifies the values of A[14:12] to use with interleave enable.
58 * [31:16] DRAM Limit Address i Bits 39-24
59 * This field defines the upper address bits of a 40 bit address
60 * that define the end of the DRAM region.
62 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
63 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
64 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
65 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
66 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
67 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
68 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
69 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
70 /* DRAM Base i Registers
82 * [ 1: 1] Write Enable
86 * [10: 8] Interleave Enable
88 * 001 = Interleave on A[12] (2 nodes)
90 * 011 = Interleave on A[12] and A[14] (4 nodes)
94 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
96 * [13:16] DRAM Base Address i Bits 39-24
97 * This field defines the upper address bits of a 40-bit address
98 * that define the start of the DRAM region.
100 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
101 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
102 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
103 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
104 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
105 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
106 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
107 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
109 /* Memory-Mapped I/O Limit i Registers
118 * [ 2: 0] Destination Node ID
128 * [ 5: 4] Destination Link ID
135 * 0 = CPU writes may be posted
136 * 1 = CPU writes must be non-posted
137 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
138 * This field defines the upp adddress bits of a 40-bit address that
139 * defines the end of a memory-mapped I/O region n
141 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
142 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
143 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
144 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
145 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
146 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
147 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
148 PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
150 /* Memory-Mapped I/O Base i Registers
159 * [ 0: 0] Read Enable
162 * [ 1: 1] Write Enable
163 * 0 = Writes disabled
165 * [ 2: 2] Cpu Disable
166 * 0 = Cpu can use this I/O range
167 * 1 = Cpu requests do not use this I/O range
169 * 0 = base/limit registers i are read/write
170 * 1 = base/limit registers i are read-only
172 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
173 * This field defines the upper address bits of a 40bit address
174 * that defines the start of memory-mapped I/O region i
176 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
177 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
178 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
179 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
180 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
181 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
182 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
183 PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
185 /* PCI I/O Limit i Registers
190 * [ 2: 0] Destination Node ID
200 * [ 5: 4] Destination Link ID
206 * [24:12] PCI I/O Limit Address i
207 * This field defines the end of PCI I/O region n
210 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
211 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
212 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
213 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
215 /* PCI I/O Base i Registers
220 * [ 0: 0] Read Enable
223 * [ 1: 1] Write Enable
224 * 0 = Writes Disabled
228 * 0 = VGA matches Disabled
229 * 1 = matches all address < 64K and where A[9:0] is in the
230 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
232 * 0 = ISA matches Disabled
233 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
234 * from matching agains this base/limit pair
236 * [24:12] PCI I/O Base i
237 * This field defines the start of PCI I/O region n
240 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
241 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
242 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
243 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
245 /* Config Base and Limit i Registers
250 * [ 0: 0] Read Enable
253 * [ 1: 1] Write Enable
254 * 0 = Writes Disabled
256 * [ 2: 2] Device Number Compare Enable
257 * 0 = The ranges are based on bus number
258 * 1 = The ranges are ranges of devices on bus 0
260 * [ 6: 4] Destination Node
270 * [ 9: 8] Destination Link
276 * [23:16] Bus Number Base i
277 * This field defines the lowest bus number in configuration region i
278 * [31:24] Bus Number Limit i
279 * This field defines the highest bus number in configuration regin i
281 PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203,
282 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
283 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
284 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
288 max = ARRAY_SIZE(register_values);
289 setup_resource_map(register_values, max);