2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2006 MSI
8 ## Written by bxshi <bingxunshi@gmail.com> for MSI.
10 ## This program is free software; you can redistribute it and/or modify
11 ## it under the terms of the GNU General Public License as published by
12 ## the Free Software Foundation; either version 2 of the License, or
13 ## (at your option) any later version.
15 ## This program is distributed in the hope that it will be useful,
16 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ## GNU General Public License for more details.
20 ## You should have received a copy of the GNU General Public License
21 ## along with this program; if not, write to the Free Software
22 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 uses CONFIG_HAVE_MP_TABLE
26 uses CONFIG_HAVE_PIRQ_TABLE
27 uses CONFIG_HAVE_ACPI_TABLES
28 uses CONFIG_HAVE_ACPI_RESUME
29 uses CONFIG_ACPI_SSDTX_NUM
30 uses CONFIG_USE_FALLBACK_IMAGE
31 uses CONFIG_HAVE_FALLBACK_BOOT
32 uses CONFIG_HAVE_HARD_RESET
33 uses CONFIG_IRQ_SLOT_COUNT
34 uses CONFIG_HAVE_OPTION_TABLE
36 uses CONFIG_MAX_PHYSICAL_CPUS
37 uses CONFIG_LOGICAL_CPUS
40 uses CONFIG_FALLBACK_SIZE
42 uses CONFIG_ROM_SECTION_SIZE
43 uses CONFIG_ROM_IMAGE_SIZE
44 uses CONFIG_ROM_SECTION_SIZE
45 uses CONFIG_ROM_SECTION_OFFSET
46 uses CONFIG_ROM_PAYLOAD
47 uses CONFIG_ROM_PAYLOAD_START
48 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
49 uses CONFIG_PRECOMPRESSED_PAYLOAD
50 uses CONFIG_PAYLOAD_SIZE
52 uses CONFIG_XIP_ROM_SIZE
53 uses CONFIG_XIP_ROM_BASE
54 uses CONFIG_STACK_SIZE
56 uses CONFIG_USE_OPTION_TABLE
57 uses CONFIG_LB_CKS_RANGE_START
58 uses CONFIG_LB_CKS_RANGE_END
59 uses CONFIG_LB_CKS_LOC
60 uses CONFIG_MAINBOARD_PART_NUMBER
61 uses CONFIG_MAINBOARD_VENDOR
63 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
64 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
65 uses COREBOOT_EXTRA_VERSION
67 uses CONFIG_TTYS0_BAUD
68 uses CONFIG_TTYS0_BASE
70 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
71 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
72 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
73 uses CONFIG_CONSOLE_SERIAL8250
74 uses CONFIG_HAVE_INIT_TIMER
77 uses CONFIG_CROSS_COMPILE
81 uses CONFIG_CONSOLE_VGA
82 uses CONFIG_PCI_ROM_RUN
83 uses CONFIG_HW_MEM_HOLE_SIZEK
84 uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
85 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
87 uses CONFIG_HT_CHAIN_UNITID_BASE
88 uses CONFIG_HT_CHAIN_END_UNITID_BASE
89 uses CONFIG_SB_HT_CHAIN_ON_BUS0
90 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
92 uses CONFIG_USE_DCACHE_RAM
93 uses CONFIG_DCACHE_RAM_BASE
94 uses CONFIG_DCACHE_RAM_SIZE
95 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
98 uses CONFIG_SERIAL_CPU_INIT
100 uses CONFIG_ENABLE_APIC_EXT_ID
101 uses CONFIG_APIC_ID_OFFSET
102 uses CONFIG_LIFT_BSP_APIC_ID
104 uses CONFIG_PCI_64BIT_PREF_MEM
106 uses CONFIG_LB_MEM_TOPK
107 uses CONFIG_USE_PRINTK_IN_CAR
114 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
116 default CONFIG_ROM_SIZE=524288
119 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
120 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
123 default CONFIG_LB_MEM_TOPK=2048
126 ## Build code for the fallback boot
128 default CONFIG_HAVE_FALLBACK_BOOT=1
131 ## Build code to reset the motherboard from coreboot
133 default CONFIG_HAVE_HARD_RESET=1
136 ## Build code to export a programmable irq routing table
138 default CONFIG_HAVE_PIRQ_TABLE=1
139 default CONFIG_IRQ_SLOT_COUNT=11
142 ## Build code to export an x86 MP table
143 ## Useful for specifying IRQ routing values
145 default CONFIG_HAVE_MP_TABLE=1
147 ## ACPI tables will be included
148 #default CONFIG_HAVE_ACPI_TABLES=1
150 #default CONFIG_ACPI_SSDTX_NUM=1
153 ## Build code to export a CMOS option table
155 default CONFIG_HAVE_OPTION_TABLE=1
158 ## Move the default coreboot cmos range off of AMD RTC registers
160 default CONFIG_LB_CKS_RANGE_START=49
161 default CONFIG_LB_CKS_RANGE_END=122
162 default CONFIG_LB_CKS_LOC=123
165 ## Build code for SMP support
166 ## Only worry about 2 micro processors
169 default CONFIG_MAX_CPUS=4
170 default CONFIG_MAX_PHYSICAL_CPUS=2
171 default CONFIG_LOGICAL_CPUS=1
173 default CONFIG_SERIAL_CPU_INIT=0
175 default CONFIG_ENABLE_APIC_EXT_ID=0
176 default CONFIG_APIC_ID_OFFSET=0x8
177 default CONFIG_LIFT_BSP_APIC_ID=1
179 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
181 #default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
183 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
185 #default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
187 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
188 #default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
190 #Opteron K8 1G HT Support
191 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
194 default CONFIG_CONSOLE_VGA=1
195 default CONFIG_PCI_ROM_RUN=1
197 #HT Unit ID offset, default is 1, the typical one
198 default CONFIG_HT_CHAIN_UNITID_BASE=0x06
200 #real SB Unit ID, default is 0x20, mean dont touch it at last
201 default CONFIG_HT_CHAIN_END_UNITID_BASE=0x01
203 #make the SB HT chain on bus 0, default is not (0)
204 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
206 #only offset for SB chain?, default is yes(1)
207 #default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
209 #allow capable device use that above 4G
210 #default CONFIG_PCI_64BIT_PREF_MEM=1
213 ## enable CACHE_AS_RAM specifics
215 default CONFIG_USE_DCACHE_RAM=1
216 default CONFIG_DCACHE_RAM_BASE=0xcc000
217 default CONFIG_DCACHE_RAM_SIZE=0x04000
218 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
219 default CONFIG_USE_INIT=0
222 ## Build code to setup a generic IOAPIC
224 default CONFIG_IOAPIC=1
227 ## Clean up the motherboard id strings
229 default CONFIG_MAINBOARD_PART_NUMBER="MS9185"
230 default CONFIG_MAINBOARD_VENDOR="MSI"
231 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
232 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
235 ### coreboot layout values
238 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
239 default CONFIG_ROM_IMAGE_SIZE = 65536
242 ## Use a small 8K stack
244 default CONFIG_STACK_SIZE=0x2000
247 ## Use a small 32K heap
249 default CONFIG_HEAP_SIZE=0x8000
252 ## Only use the option table in a normal image
254 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
257 ## Coreboot C code runs at this location in RAM
259 default CONFIG_RAMBASE=0x00100000
262 ## Load the payload from the ROM
264 default CONFIG_ROM_PAYLOAD = 1
267 ### Defaults of options that you may want to override in the target config file
271 ## The default compiler
273 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
277 ## Disable the gdb stub by default
279 default CONFIG_GDB_STUB=0
282 ## The Serial Console
284 default CONFIG_USE_PRINTK_IN_CAR=1
286 # To Enable the Serial Console
287 default CONFIG_CONSOLE_SERIAL8250=1
289 ## Select the serial console baud rate
290 default CONFIG_TTYS0_BAUD=115200
291 #default CONFIG_TTYS0_BAUD=57600
292 #default CONFIG_TTYS0_BAUD=38400
293 #default CONFIG_TTYS0_BAUD=19200
294 #default CONFIG_TTYS0_BAUD=9600
295 #default CONFIG_TTYS0_BAUD=4800
296 #default CONFIG_TTYS0_BAUD=2400
297 #default CONFIG_TTYS0_BAUD=1200
299 # Select the serial console base port
300 default CONFIG_TTYS0_BASE=0x3f8
302 # Select the serial protocol
303 # This defaults to 8 data bits, 1 stop bit, and no parity
304 default CONFIG_TTYS0_LCS=0x3
307 ### Select the coreboot loglevel
309 ## EMERG 1 system is unusable
310 ## ALERT 2 action must be taken immediately
311 ## CRIT 3 critical conditions
312 ## ERR 4 error conditions
313 ## WARNING 5 warning conditions
314 ## NOTICE 6 normal but significant condition
315 ## INFO 7 informational
316 ## CONFIG_DEBUG 8 debug-level messages
317 ## SPEW 9 Way too many details
319 ## Request this level of debugging output
320 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
321 ## At a maximum only compile in this level of debugging
322 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
325 ## Select power on after power fail setting
326 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"