2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2006 AMD
5 ## Written by Yinghai Lu <yinghailu@gmail.com> for AMD.
7 ## Copyright (C) 2006 MSI
8 ## Written by bxshi <bingxunshi@gmail.com> for MSI.
10 ## This program is free software; you can redistribute it and/or modify
11 ## it under the terms of the GNU General Public License as published by
12 ## the Free Software Foundation; either version 2 of the License, or
13 ## (at your option) any later version.
15 ## This program is distributed in the hope that it will be useful,
16 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
17 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 ## GNU General Public License for more details.
20 ## You should have received a copy of the GNU General Public License
21 ## along with this program; if not, write to the Free Software
22 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
26 default CONFIG_XIP_ROM_SIZE = 64 * 1024
27 include /config/nofailovercalculation.lb
32 ## Build the objects we have code for in this directory.
39 #needed by irq_tables and mptable and acpi_tables
42 if CONFIG_GENERATE_MP_TABLE
46 if CONFIG_GENERATE_PIRQ_TABLE
51 # compile cache_as_ram.c to auto.o
52 makerule ./cache_as_ram_auto.o
53 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
54 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
58 #compile cache_as_ram.c to auto.inc
59 makerule ./cache_as_ram_auto.inc
60 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
61 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
62 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
63 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
68 ## Build our 16 bit and 32 bit coreboot entry code
71 if CONFIG_USE_FALLBACK_IMAGE
72 mainboardinit cpu/x86/16bit/entry16.inc
73 ldscript /cpu/x86/16bit/entry16.lds
76 mainboardinit cpu/x86/32bit/entry32.inc
78 ldscript /cpu/x86/32bit/entry32.lds
82 ldscript /cpu/amd/car/cache_as_ram.lds
86 ## Build our reset vector (This is where coreboot is entered)
88 if CONFIG_USE_FALLBACK_IMAGE
89 mainboardinit cpu/x86/16bit/reset16.inc
90 ldscript /cpu/x86/16bit/reset16.lds
92 mainboardinit cpu/x86/32bit/reset32.inc
93 ldscript /cpu/x86/32bit/reset32.lds
97 ## Include an id string (For safe flashing)
99 mainboardinit arch/i386/lib/id.inc
100 ldscript /arch/i386/lib/id.lds
103 ## Setup Cache-As-Ram
105 mainboardinit cpu/amd/car/cache_as_ram.inc
108 ### This is the early phase of coreboot startup
109 ### Things are delicate and we test to see if we should
110 ### failover to another image.
112 if CONFIG_USE_FALLBACK_IMAGE
113 ldscript /arch/i386/lib/failover.lds
117 ### O.k. We aren't just an intermediary anymore!
124 initobject cache_as_ram_auto.o
126 mainboardinit ./cache_as_ram_auto.inc
130 ## Include the secondary Configuration files
134 # sample config for amd/serengeti_cheetah
135 chip northbridge/amd/amdk8/root_complex
136 device apic_cluster 0 on
137 chip cpu/amd/socket_F
141 device pci_domain 0 on
142 chip northbridge/amd/amdk8
143 device pci 18.0 on end
144 device pci 18.0 on end
145 device pci 18.0 on # northbridge
147 chip southbridge/broadcom/bcm5780 # HT2000
148 device pci 0.0 on end # PXB 1 0x0130
149 device pci 1.0 on # PXB 2 0x0130
150 device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
151 device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
153 device pci 2.0 on end # PCI E 1 #0x0132
154 device pci 3.0 on end # PCI E 2
155 device pci 4.0 on end # PCI E 3
156 device pci 5.0 on end # PCI E 4
158 chip southbridge/broadcom/bcm5785 # HT1000
159 device pci 0.0 on # HT PXB 0x0036
160 device pci d.0 on end # PPBX 0x0104
161 device pci e.0 on end # SATA 0x024a
162 device pci e.1 on end # SATA 0x024a bx_a001
163 device pci e.2 on end # SATA 0x024a bx_a001
164 device pci e.3 on end # SATA 0x024a bx_a001
166 device pci 1.0 on # Legacy pci main 0x0205
168 device pci 1.1 on end # IDE 0x0214
169 device pci 1.2 on # LPC 0x0234
170 chip superio/nsc/pc87417
171 device pnp 2e.0 off # Floppy
176 device pnp 2e.1 off # Parallel Port
180 device pnp 2e.2 off # Com 2
184 device pnp 2e.3 on # Com 1
188 device pnp 2e.4 off end # SWC
189 device pnp 2e.5 off end # Mouse
190 device pnp 2e.6 on # Keyboard
195 device pnp 2e.7 off end # GPIO
196 device pnp 2e.f off end # XBUS
197 device pnp 2e.10 on #RTC
203 device pci 1.3 on end # WDTimer 0x0238
204 device pci 1.4 on end # XIOAPIC0 0x0235
205 device pci 1.5 on end # XIOAPIC1
206 device pci 1.6 on end # XIOAPIC2
207 device pci 2.0 on end # USB 0x0223
208 device pci 2.1 on end # USB
209 device pci 2.2 on end # USB
210 device pci 3.0 on end # it is in bcm5785_0 bus
212 end # device pci 18.0
213 device pci 18.1 on end
214 device pci 18.2 on end
215 device pci 18.3 on end
218 # chip drivers/generic/debug
219 # device pnp 0.0 off end # chip name
220 # device pnp 0.1 on end # pci_regs_all
221 # device pnp 0.2 off end # mem
222 # device pnp 0.3 off end # cpuid
223 # device pnp 0.4 off end # smbus_regs_all
224 # device pnp 0.5 off end # dual core msr
225 # device pnp 0.6 off end # cache size
226 # device pnp 0.7 off end # tsc