Please bear with me - another rename checkin. This qualifies as trivial, no
[coreboot.git] / src / mainboard / msi / ms7260 / irq_tables.c
1 /*
2  * This file is part of the coreboot project.
3  *
4  * Copyright (C) 2007 AMD
5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, write to the Free Software
19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
20  */
21
22 #include <console/console.h>
23 #include <device/pci.h>
24 #include <string.h>
25 #include <stdint.h>
26 #include <arch/pirq_routing.h>
27 #include <cpu/amd/amdk8_sysconf.h>
28
29 static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
30                             uint8_t devfn, uint8_t link0, uint16_t bitmap0,
31                             uint8_t link1, uint16_t bitmap1, uint8_t link2,
32                             uint16_t bitmap2, uint8_t link3, uint16_t bitmap3,
33                             uint8_t slot, uint8_t rfu)
34 {
35         pirq_info->bus = bus;
36         pirq_info->devfn = devfn;
37         pirq_info->irq[0].link = link0;
38         pirq_info->irq[0].bitmap = bitmap0;
39         pirq_info->irq[1].link = link1;
40         pirq_info->irq[1].bitmap = bitmap1;
41         pirq_info->irq[2].link = link2;
42         pirq_info->irq[2].bitmap = bitmap2;
43         pirq_info->irq[3].link = link3;
44         pirq_info->irq[3].bitmap = bitmap3;
45         pirq_info->slot = slot;
46         pirq_info->rfu = rfu;
47 }
48
49 extern unsigned char bus_isa;
50 extern unsigned char bus_mcp55[8];      // 1
51
52 unsigned long write_pirq_routing_table(unsigned long addr)
53 {
54         struct irq_routing_table *pirq;
55         struct irq_info *pirq_info;
56         unsigned int slot_num, sbdn;
57         uint8_t *v;
58         uint8_t sum = 0;
59         int i;
60
61         /* Will find out all bus num and apic that share with mptable.c
62          * and mptable.c and acpi_tables.c.
63          */
64         get_bus_conf();
65         sbdn = sysconf.sbdn;
66
67         /* Align the table to be 16 byte aligned. */
68         addr += 15;
69         addr &= ~15;
70
71         /* This table must be betweeen 0xf0000 and 0x100000. */
72         printk_info("Writing IRQ routing tables to 0x%x...", addr);
73
74         pirq = (void *)(addr);
75         v = (uint8_t *)(addr);
76
77         pirq->signature = PIRQ_SIGNATURE;
78         pirq->version = PIRQ_VERSION;
79         pirq->rtr_bus = bus_mcp55[0];
80         pirq->rtr_devfn = ((sbdn + 6) << 3) | 0;
81         pirq->exclusive_irqs = 0;
82         pirq->rtr_vendor = 0x10de;
83         pirq->rtr_device = 0x0370; /* TODO: Hm, getpir suggests 0x0364 !? */
84         pirq->miniport_data = 0;
85
86         memset(pirq->rfu, 0, sizeof(pirq->rfu));
87
88         pirq_info = (void *)(&pirq->checksum + 1);
89         slot_num = 0;
90
91         /* PCI bridge (00:06.0) */
92         write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
93                         0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
94         pirq_info++;
95         slot_num++;
96
97         pirq->size = 32 + 16 * slot_num;
98
99         for (i = 0; i < pirq->size; i++)
100                 sum += v[i];
101
102         sum = pirq->checksum - sum;
103
104         if (sum != pirq->checksum)
105                 pirq->checksum = sum;
106
107         printk_info("done.\n");
108
109         return (unsigned long)pirq_info;
110 }