2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 include /config/failovercalculation.lb
26 object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables).
27 if HAVE_MP_TABLE object mptable.o end
28 if HAVE_PIRQ_TABLE object irq_tables.o end
32 makerule ./cache_as_ram_auto.o
33 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
34 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
37 makerule ./cache_as_ram_auto.inc
38 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
39 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
40 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
41 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
47 if CONFIG_AP_CODE_IN_CAR
49 depends "$(MAINBOARD)/apc_auto.c option_table.h"
50 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
52 ldscript /arch/i386/init/ldscript_apc.lb
58 mainboardinit cpu/x86/16bit/entry16.inc
59 ldscript /cpu/x86/16bit/entry16.lds
63 mainboardinit cpu/x86/16bit/entry16.inc
64 ldscript /cpu/x86/16bit/entry16.lds
68 mainboardinit cpu/x86/32bit/entry32.inc
71 ldscript /cpu/x86/32bit/entry32.lds
74 ldscript /cpu/amd/car/cache_as_ram.lds
79 mainboardinit cpu/x86/16bit/reset16.inc
80 ldscript /cpu/x86/16bit/reset16.lds
82 mainboardinit cpu/x86/32bit/reset32.inc
83 ldscript /cpu/x86/32bit/reset32.lds
87 mainboardinit cpu/x86/16bit/reset16.inc
88 ldscript /cpu/x86/16bit/reset16.lds
90 mainboardinit cpu/x86/32bit/reset32.inc
91 ldscript /cpu/x86/32bit/reset32.lds
95 mainboardinit southbridge/nvidia/mcp55/id.inc
96 ldscript /southbridge/nvidia/mcp55/id.lds
98 # ROMSTRAP table for MCP55.
100 if USE_FAILOVER_IMAGE
101 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
102 ldscript /southbridge/nvidia/mcp55/romstrap.lds
105 if USE_FALLBACK_IMAGE
106 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
107 ldscript /southbridge/nvidia/mcp55/romstrap.lds
111 mainboardinit cpu/amd/car/cache_as_ram.inc
113 if HAVE_FAILOVER_BOOT
114 if USE_FAILOVER_IMAGE
115 ldscript /arch/i386/lib/failover_failover.lds
118 if USE_FALLBACK_IMAGE
119 ldscript /arch/i386/lib/failover.lds
124 initobject cache_as_ram_auto.o
126 mainboardinit ./cache_as_ram_auto.inc
131 chip northbridge/amd/amdk8/root_complex # Root complex
132 device apic_cluster 0 on # APIC cluster
133 chip cpu/amd/socket_AM2 # CPU
134 device apic 0 on end # APIC
137 device pci_domain 0 on # PCI domain
138 chip northbridge/amd/amdk8 # Northbridge / mc0
140 # Devices on link 0, link 0 == LDT 0
141 chip southbridge/nvidia/mcp55 # Southbridge
142 device pci 0.0 on end # HT
143 device pci 1.0 on # LPC
144 chip superio/winbond/w83627ehg # Super I/O
145 device pnp 4e.0 on # Floppy
150 device pnp 4e.1 on # Parallel port
154 device pnp 4e.2 on # Com1
158 device pnp 4e.3 on # Com2 / IrDA
162 device pnp 4e.5 on # PS/2 keyboard
165 irq 0x70 = 1 # PS/2 keyboard IRQ
166 irq 0x72 = 12 # PS/2 mouse IRQ
168 device pnp 4e.6 off # Serial flash interface
171 device pnp 4e.7 off # GPIO1/6, game port, MIDI port
172 # io 0x60 = 0x220 # Datasheet: 0x201
173 # io 0x62 = 0x300 # Datasheet: 0x330
176 device pnp 4e.8 off # WDTO#, PLED
178 device pnp 4e.9 off # GPIO2/3/4/5, SUSLED
180 device pnp 4e.a off # ACPI
182 device pnp 4e.b on # HWM (for lm-sensors)
187 device pci 1.1 on # SM 0
188 chip drivers/generic/generic # DIMM 0-0-0
191 chip drivers/generic/generic # DIMM 0-0-1
194 chip drivers/generic/generic # DIMM 0-1-0
197 chip drivers/generic/generic # DIMM 0-1-1
201 # chip drivers/generic/generic # DIMM 1-0-0
202 # device i2c 54 on end
204 # chip drivers/generic/generic # DIMM 1-0-1
205 # device i2c 55 on end
207 # chip drivers/generic/generic # DIMM 1-1-0
208 # device i2c 56 on end
210 # chip drivers/generic/generic # DIMM 1-1-1
211 # device i2c 57 on end
214 # TODO: Check if the stuff below is correct / needed.
215 device pci 1.1 on # SM 1
216 # PCI device SMBus address will depend on addon PCI device,
217 # do we need to scan_smbus_bus?
219 # chip drivers/generic/generic # PCIXA Slot1
220 # device i2c 50 on end
222 # chip drivers/generic/generic # PCIXB Slot1
223 # device i2c 51 on end
225 # chip drivers/generic/generic # PCIXB Slot2
226 # device i2c 52 on end
228 # chip drivers/generic/generic # PCI Slot1
229 # device i2c 53 on end
231 # chip drivers/generic/generic # Master MCP55 PCI-E
232 # device i2c 54 on end
234 # chip drivers/generic/generic # Slave MCP55 PCI-E
235 # device i2c 55 on end
237 chip drivers/generic/generic # MAC EEPROM
241 device pci 2.0 on end # USB 1.1
242 device pci 2.1 on end # USB 2
243 device pci 4.0 on end # IDE
244 device pci 5.0 on end # SATA 0
245 device pci 5.1 on end # SATA 1
246 device pci 5.2 off end # SATA 2 (N/A on this board)
247 device pci 6.0 on end # PCI
248 device pci 6.1 on end # AZA (HD Audio)
249 device pci 8.0 on end # NIC
250 device pci 9.0 off end # NIC (N/A on this board)
251 device pci a.0 off end # PCI E 5 (N/A on this board?)
252 device pci b.0 on end # PCI E 4
253 device pci c.0 on end # PCI E 3
254 device pci d.0 on end # PCI E 2
255 device pci e.0 on end # PCI E 1
256 device pci f.0 on end # PCI E 0
257 register "ide0_enable" = "1"
258 register "sata0_enable" = "1"
259 register "sata1_enable" = "1"
260 # TODO: Check the two lines below.
261 register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1
262 register "mac_eeprom_addr" = "0x51"
265 device pci 18.0 on end # Link 1
266 device pci 18.0 on end
267 device pci 18.1 on end
268 device pci 18.2 on end
269 device pci 18.3 on end
274 # chip drivers/generic/debug
275 # device pnp 0.0 off end # chip name
276 # device pnp 0.1 on end # pci_regs_all
277 # device pnp 0.2 on end # mem
278 # device pnp 0.3 off end # cpuid
279 # device pnp 0.4 on end # smbus_regs_all
280 # device pnp 0.5 off end # dual core msr
281 # device pnp 0.6 off end # cache size
282 # device pnp 0.7 off end # tsc
283 # device pnp 0.8 off end # io
284 # device pnp 0.9 off end # io