2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 default ROM_SECTION_SIZE = FAILOVER_SIZE
23 default ROM_SECTION_OFFSET = (ROM_SIZE - FAILOVER_SIZE)
26 default ROM_SECTION_SIZE = FALLBACK_SIZE
27 default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
29 default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE)
30 default ROM_SECTION_OFFSET = 0
34 default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
35 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
36 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
37 default XIP_ROM_SIZE = 65536
40 default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
43 default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
45 default XIP_ROM_BASE = (_ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
52 object get_bus_conf.o # Needed by irq_tables and mptable (and acpi_tables).
53 if HAVE_MP_TABLE object mptable.o end
54 if HAVE_PIRQ_TABLE object irq_tables.o end
58 makerule ./cache_as_ram_auto.o
59 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
60 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
63 makerule ./cache_as_ram_auto.inc
64 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
65 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
66 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
67 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
73 if CONFIG_AP_CODE_IN_CAR
75 depends "$(MAINBOARD)/apc_auto.c option_table.h"
76 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/apc_auto.c -o $@"
78 ldscript /arch/i386/init/ldscript_apc.lb
84 mainboardinit cpu/x86/16bit/entry16.inc
85 ldscript /cpu/x86/16bit/entry16.lds
89 mainboardinit cpu/x86/16bit/entry16.inc
90 ldscript /cpu/x86/16bit/entry16.lds
94 mainboardinit cpu/x86/32bit/entry32.inc
97 ldscript /cpu/x86/32bit/entry32.lds
100 ldscript /cpu/amd/car/cache_as_ram.lds
103 if HAVE_FAILOVER_BOOT
104 if USE_FAILOVER_IMAGE
105 mainboardinit cpu/x86/16bit/reset16.inc
106 ldscript /cpu/x86/16bit/reset16.lds
108 mainboardinit cpu/x86/32bit/reset32.inc
109 ldscript /cpu/x86/32bit/reset32.lds
112 if USE_FALLBACK_IMAGE
113 mainboardinit cpu/x86/16bit/reset16.inc
114 ldscript /cpu/x86/16bit/reset16.lds
116 mainboardinit cpu/x86/32bit/reset32.inc
117 ldscript /cpu/x86/32bit/reset32.lds
121 mainboardinit southbridge/nvidia/mcp55/id.inc
122 ldscript /southbridge/nvidia/mcp55/id.lds
124 # ROMSTRAP table for MCP55.
125 if HAVE_FAILOVER_BOOT
126 if USE_FAILOVER_IMAGE
127 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
128 ldscript /southbridge/nvidia/mcp55/romstrap.lds
131 if USE_FALLBACK_IMAGE
132 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
133 ldscript /southbridge/nvidia/mcp55/romstrap.lds
137 mainboardinit cpu/amd/car/cache_as_ram.inc
139 if HAVE_FAILOVER_BOOT
140 if USE_FAILOVER_IMAGE
141 ldscript /arch/i386/lib/failover_failover.lds
144 if USE_FALLBACK_IMAGE
145 ldscript /arch/i386/lib/failover.lds
150 initobject cache_as_ram_auto.o
152 mainboardinit ./cache_as_ram_auto.inc
157 chip northbridge/amd/amdk8/root_complex # Root complex
158 device apic_cluster 0 on # APIC cluster
159 chip cpu/amd/socket_AM2 # CPU
160 device apic 0 on end # APIC
163 device pci_domain 0 on # PCI domain
164 chip northbridge/amd/amdk8 # Northbridge / mc0
166 # Devices on link 0, link 0 == LDT 0
167 chip southbridge/nvidia/mcp55 # Southbridge
168 device pci 0.0 on end # HT
169 device pci 1.0 on # LPC
170 chip superio/winbond/w83627ehg # Super I/O
171 device pnp 4e.0 on # Floppy
176 device pnp 4e.1 on # Parallel port
180 device pnp 4e.2 on # Com1
184 device pnp 4e.3 on # Com2 / IrDA
188 device pnp 4e.5 on # PS/2 keyboard
191 irq 0x70 = 1 # PS/2 keyboard IRQ
192 irq 0x72 = 12 # PS/2 mouse IRQ
194 device pnp 4e.6 off # Serial flash interface
197 device pnp 4e.7 off # GPIO1/6, game port, MIDI port
198 # io 0x60 = 0x220 # Datasheet: 0x201
199 # io 0x62 = 0x300 # Datasheet: 0x330
202 device pnp 4e.8 off # WDTO#, PLED
204 device pnp 4e.9 off # GPIO2/3/4/5, SUSLED
206 device pnp 4e.a off # ACPI
208 device pnp 4e.b on # HWM (for lm-sensors)
213 device pci 1.1 on # SM 0
214 chip drivers/generic/generic # DIMM 0-0-0
217 chip drivers/generic/generic # DIMM 0-0-1
220 chip drivers/generic/generic # DIMM 0-1-0
223 chip drivers/generic/generic # DIMM 0-1-1
227 # chip drivers/generic/generic # DIMM 1-0-0
228 # device i2c 54 on end
230 # chip drivers/generic/generic # DIMM 1-0-1
231 # device i2c 55 on end
233 # chip drivers/generic/generic # DIMM 1-1-0
234 # device i2c 56 on end
236 # chip drivers/generic/generic # DIMM 1-1-1
237 # device i2c 57 on end
240 # TODO: Check if the stuff below is correct / needed.
241 device pci 1.1 on # SM 1
242 # PCI device SMBus address will depend on addon PCI device,
243 # do we need to scan_smbus_bus?
245 # chip drivers/generic/generic # PCIXA Slot1
246 # device i2c 50 on end
248 # chip drivers/generic/generic # PCIXB Slot1
249 # device i2c 51 on end
251 # chip drivers/generic/generic # PCIXB Slot2
252 # device i2c 52 on end
254 # chip drivers/generic/generic # PCI Slot1
255 # device i2c 53 on end
257 # chip drivers/generic/generic # Master MCP55 PCI-E
258 # device i2c 54 on end
260 # chip drivers/generic/generic # Slave MCP55 PCI-E
261 # device i2c 55 on end
263 chip drivers/generic/generic # MAC EEPROM
267 device pci 2.0 on end # USB 1.1
268 device pci 2.1 on end # USB 2
269 device pci 4.0 on end # IDE
270 device pci 5.0 on end # SATA 0
271 device pci 5.1 on end # SATA 1
272 device pci 5.2 off end # SATA 2 (N/A on this board)
273 device pci 6.0 on end # PCI
274 device pci 6.1 on end # AZA (HD Audio)
275 device pci 8.0 on end # NIC
276 device pci 9.0 off end # NIC (N/A on this board)
277 device pci a.0 off end # PCI E 5 (N/A on this board?)
278 device pci b.0 on end # PCI E 4
279 device pci c.0 on end # PCI E 3
280 device pci d.0 on end # PCI E 2
281 device pci e.0 on end # PCI E 1
282 device pci f.0 on end # PCI E 0
283 register "ide0_enable" = "1"
284 register "sata0_enable" = "1"
285 register "sata1_enable" = "1"
286 # TODO: Check the two lines below.
287 register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1
288 register "mac_eeprom_addr" = "0x51"
291 device pci 18.0 on end # Link 1
292 device pci 18.0 on end
293 device pci 18.1 on end
294 device pci 18.2 on end
295 device pci 18.3 on end
300 # chip drivers/generic/debug
301 # device pnp 0.0 off end # chip name
302 # device pnp 0.1 on end # pci_regs_all
303 # device pnp 0.2 on end # mem
304 # device pnp 0.3 off end # cpuid
305 # device pnp 0.4 on end # smbus_regs_all
306 # device pnp 0.5 off end # dual core msr
307 # device pnp 0.6 off end # cache size
308 # device pnp 0.7 off end # tsc
309 # device pnp 0.8 off end # io
310 # device pnp 0.9 off end # io