2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
8 * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)
27 /* Used by raminit. */
28 #define QRANK_DIMM_SUPPORT 1
30 #if CONFIG_LOGICAL_CPUS == 1
31 #define SET_NB_CFG_54 1
36 #include <device/pci_def.h>
38 #include <device/pnp_def.h>
39 #include <arch/romcc_io.h>
40 #include <cpu/x86/lapic.h>
41 #include <pc80/mc146818rtc.h>
42 #include "cpu/x86/lapic/boot_cpu.c"
43 #include "northbridge/amd/amdk8/reset_test.c"
44 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
46 #include <cpu/amd/model_fxx_rev.h>
47 #include <console/console.h>
48 #include "northbridge/amd/amdk8/incoherent_ht.c"
49 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
50 #include "northbridge/amd/amdk8/raminit.h"
51 #include "cpu/amd/model_fxx/apic_timer.c"
52 #include "lib/delay.c"
53 #include "northbridge/amd/amdk8/debug.c"
54 #include "cpu/x86/mtrr/earlymtrr.c"
55 #include "cpu/x86/bist.h"
56 #include "northbridge/amd/amdk8/setup_resource_map.c"
57 #include "northbridge/amd/amdk8/coherent_ht.c"
58 #include "cpu/amd/dualcore/dualcore.c"
60 static void memreset_setup(void)
62 /* FIXME: Nothing to do? */
65 static void memreset(int controllers, const struct mem_controller *ctrl)
67 /* FIXME: Nothing to do? */
70 static inline void activate_spd_rom(const struct mem_controller *ctrl)
72 /* FIXME: Nothing to do? */
75 static inline int spd_read_byte(unsigned device, unsigned address)
77 return smbus_read_byte(device, address);
80 #include "northbridge/amd/amdk8/raminit.c"
81 #include "lib/generic_sdram.c"
82 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
83 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
85 #include "cpu/amd/car/post_cache_as_ram.c"
86 #include "cpu/amd/model_fxx/init_cpus.c"
88 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
89 #include "northbridge/amd/amdk8/early_ht.c"
91 static void sio_setup(void)
96 /* Subject decoding */
97 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
99 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
101 /* LPC Positive Decode 0 */
102 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
103 /* Serial 0, Serial 1 */
104 dword |= (1 << 0) | (1 << 1);
105 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
108 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
110 static const uint16_t spd_addr[] = {
111 (0xa << 3) | 0, (0xa << 3) | 1, 0, 0,
118 unsigned bsp_apicid = 0;
120 struct mem_controller ctrl[8];
123 if (!cpu_init_detectedx && boot_cpu()) {
124 /* Nothing special needs to be done to find bus 0 */
125 /* Allow the HT devices to be found */
126 enumerate_ht_chain();
130 /* Setup the ck804 */
135 bsp_apicid = init_cpus(cpu_init_detectedx);
138 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
142 /* Halt if there was a built in self test failure */
143 report_bist_failure(bist);
146 dump_pci_device(PCI_DEV(0, 0x18, 0));
149 needs_reset = setup_coherent_ht_domain();
151 wait_all_core0_started();
152 #if CONFIG_LOGICAL_CPUS==1
153 // It is said that we should start core1 after all core0 launched
155 wait_all_other_cores_started(bsp_apicid);
158 needs_reset |= ht_setup_chains_x();
160 needs_reset |= ck804_early_setup_x();
163 print_info("ht reset -\n");
167 allow_all_aps_stop(bsp_apicid);
170 //It's the time to set ctrl now;
171 fill_mem_ctrl(nodes, ctrl, spd_addr);
176 dump_spd_registers(&ctrl[0]);
177 dump_smbus_registers();
181 sdram_initialize(nodes, ctrl);