src/mainboard/msi/ms7135/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
   7  * (Thanks to LSRA University of Mannheim for their support)
   8  * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #include <stdint.h>
  26 #include <string.h>
  27 #include <device/pci_def.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <arch/romcc_io.h>
  31 #include <cpu/x86/lapic.h>
  32 #include <pc80/mc146818rtc.h>
  33 #include "cpu/x86/lapic/boot_cpu.c"
  34 #include "northbridge/amd/amdk8/reset_test.c"
  35 #include "superio/winbond/w83627thg/early_serial.c"
  36 #include <cpu/amd/model_fxx_rev.h>
  37 #include <console/console.h>
  38 #include "northbridge/amd/amdk8/incoherent_ht.c"
  39 #include "southbridge/nvidia/ck804/early_smbus.h"
  40 #include "northbridge/amd/amdk8/raminit.h"
  41 #include "cpu/amd/model_fxx/apic_timer.c"
  42 #include "lib/delay.c"
  43 #include "northbridge/amd/amdk8/debug.c"
  44 #include "cpu/x86/mtrr/earlymtrr.c"
  45 #include "cpu/x86/bist.h"
  46 #include "northbridge/amd/amdk8/setup_resource_map.c"
  47 #include "northbridge/amd/amdk8/coherent_ht.c"
  48 #include "cpu/amd/dualcore/dualcore.c"
  49 #include <spd.h>
  50
  51 #if CONFIG_HAVE_OPTION_TABLE
  52 #include "option_table.h"
  53 #endif
  54
  55 #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
  56
  57 static void memreset(int controllers, const struct mem_controller *ctrl) { }
  58 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  59
  60 static inline int spd_read_byte(unsigned device, unsigned address)
  61 {
  62         return smbus_read_byte(device, address);
  63 }
  64
  65 #include "northbridge/amd/amdk8/raminit.c"
  66 #include "lib/generic_sdram.c"
  67 #include "southbridge/nvidia/ck804/early_setup_ss.h"
  68 #include "southbridge/nvidia/ck804/early_setup_car.c"
  69 #include "cpu/amd/car/post_cache_as_ram.c"
  70 #include "cpu/amd/model_fxx/init_cpus.c"
  71 #include "northbridge/amd/amdk8/early_ht.c"
  72
  73 static void ms7135_set_ram_voltage(void)
  74 {
  75         u8 b;
  76         b = read_option(ram_voltage, 0);
  77         if (b > 4) /* default if above 2.70v */
  78                 b = 0;
  79         printk(BIOS_INFO, "setting RAM voltage %08x\n", b);
  80         ck804_smbus_write_byte(1, 0x2f, 0x00, b);
  81 }
  82
  83 static void ms7135_set_nf4_voltage(void)
  84 {
  85         u8 b;
  86         b = read_option(nf4_voltage, 0);
  87         if (b > 2) /* default if above 1.60v */
  88                 b = 0;
  89         b |= 0x10;
  90         printk(BIOS_INFO, "setting NF4 voltage %08x\n", b);
  91         ck804_smbus_write_byte(1, 0x2f, 0x02, b);
  92 }
  93
  94 static void sio_setup(void)
  95 {
  96         u32 dword;
  97         u8 byte;
  98
  99         /* Subject decoding */
 100         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
 101         byte |= 0x20;
 102         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
 103
 104         /* LPC Positive Decode 0 */
 105         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
 106         /* Serial 0, Serial 1 */
 107         dword |= (1 << 0) | (1 << 1);
 108         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
 109 }
 110
 111 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 112 {
 113         static const u16 spd_addr[] = {
 114                 DIMM0, DIMM1, 0, 0,
 115                 0, 0, 0, 0,
 116                 0, 0, 0, 0,
 117                 0, 0, 0, 0,
 118         };
 119
 120         int needs_reset;
 121         unsigned bsp_apicid = 0, nodes;
 122         struct mem_controller ctrl[8];
 123
 124         if (!cpu_init_detectedx && boot_cpu()) {
 125                 /* Nothing special needs to be done to find bus 0 */
 126                 /* Allow the HT devices to be found */
 127                 enumerate_ht_chain();
 128                 sio_setup();
 129         }
 130
 131         if (bist == 0)
 132                 bsp_apicid = init_cpus(cpu_init_detectedx);
 133
 134         w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 135         console_init();
 136
 137         /* Halt if there was a built in self test failure */
 138         report_bist_failure(bist);
 139
 140         needs_reset = setup_coherent_ht_domain();
 141
 142         wait_all_core0_started();
 143 #if CONFIG_LOGICAL_CPUS==1
 144         // It is said that we should start core1 after all core0 launched
 145         start_other_cores();
 146         wait_all_other_cores_started(bsp_apicid);
 147 #endif
 148
 149         needs_reset |= ht_setup_chains_x();
 150         needs_reset |= ck804_early_setup_x();
 151         if (needs_reset) {
 152                 print_info("ht reset -\n");
 153                 soft_reset();
 154         }
 155
 156         allow_all_aps_stop(bsp_apicid);
 157
 158         nodes = get_nodes();
 159         //It's the time to set ctrl now;
 160         fill_mem_ctrl(nodes, ctrl, spd_addr);
 161
 162         enable_smbus();
 163
 164         ms7135_set_nf4_voltage();
 165         ms7135_set_ram_voltage();
 166
 167 #if CONFIG_DEBUG_SMBUS
 168         dump_spd_registers(&ctrl[0]);
 169         dump_smbus_registers();
 170 #endif
 171
 172         sdram_initialize(nodes, ctrl);
 173
 174         post_cache_as_ram();
 175 }