src/mainboard/msi/ms7135/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
   7  * (Thanks to LSRA University of Mannheim for their support)
   8  * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #define ASSEMBLY 1
  26 #define __PRE_RAM__
  27
  28 #define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)
  29
  30 /* Used by raminit. */
  31 #define QRANK_DIMM_SUPPORT 1
  32
  33 #if CONFIG_LOGICAL_CPUS == 1
  34 #define SET_NB_CFG_54 1
  35 #endif
  36
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <device/pci_def.h>
  40 #include <arch/io.h>
  41 #include <device/pnp_def.h>
  42 #include <arch/romcc_io.h>
  43 #include <cpu/x86/lapic.h>
  44 #include "option_table.h"
  45 #include "pc80/mc146818rtc_early.c"
  46 #include "cpu/x86/lapic/boot_cpu.c"
  47 #include "northbridge/amd/amdk8/reset_test.c"
  48 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  49
  50 #if CONFIG_USE_FAILOVER_IMAGE == 0
  51
  52 /* Used by ck804_early_setup(). */
  53 #define CK804_NUM 1
  54 #define CK804_USE_NIC 1
  55 #define CK804_USE_ACI 1
  56
  57 #include <cpu/amd/model_fxx_rev.h>
  58 #include "pc80/serial.c"
  59 #include "arch/i386/lib/console.c"
  60 #include "lib/ramtest.c"
  61 #include "northbridge/amd/amdk8/incoherent_ht.c"
  62 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  63 #include "northbridge/amd/amdk8/raminit.h"
  64 #include "cpu/amd/model_fxx/apic_timer.c"
  65 #include "lib/delay.c"
  66 #include "northbridge/amd/amdk8/debug.c"
  67 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  68 #include "cpu/x86/bist.h"
  69 #include "northbridge/amd/amdk8/setup_resource_map.c"
  70 #include "northbridge/amd/amdk8/coherent_ht.c"
  71 #include "cpu/amd/dualcore/dualcore.c"
  72
  73 static void memreset_setup(void)
  74 {
  75         /* FIXME: Nothing to do? */
  76 }
  77
  78 static void memreset(int controllers, const struct mem_controller *ctrl)
  79 {
  80         /* FIXME: Nothing to do? */
  81 }
  82
  83 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  84 {
  85         /* FIXME: Nothing to do? */
  86 }
  87
  88 static inline int spd_read_byte(unsigned device, unsigned address)
  89 {
  90         return smbus_read_byte(device, address);
  91 }
  92
  93 #include "northbridge/amd/amdk8/raminit.c"
  94 #include "lib/generic_sdram.c"
  95 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  96 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  97 #include "cpu/amd/car/copy_and_run.c"
  98 #include "cpu/amd/car/post_cache_as_ram.c"
  99 #include "cpu/amd/model_fxx/init_cpus.c"
 100
 101 #endif  /* CONFIG_USE_FAILOVER_IMAGE */
 102
 103 #if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) \
 104         || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 105
 106 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 107 #include "northbridge/amd/amdk8/early_ht.c"
 108
 109 static void sio_setup(void)
 110 {
 111         unsigned value;
 112         uint32_t dword;
 113         uint8_t byte;
 114
 115         /* Subject decoding */
 116         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
 117         byte |= 0x20;
 118         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
 119
 120         /* LPC Positive Decode 0 */
 121         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
 122         /* Serial 0, Serial 1 */
 123         dword |= (1 << 0) | (1 << 1);
 124         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
 125 }
 126
 127 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 128 {
 129         unsigned last_boot_normal_x = last_boot_normal();
 130
 131         /* Is this a CPU only reset? Or is this a secondary CPU? */
 132         if ((cpu_init_detectedx) || (!boot_cpu())) {
 133                 if (last_boot_normal_x) {
 134                         goto normal_image;
 135                 } else {
 136                         goto fallback_image;
 137                 }
 138         }
 139
 140         /* Nothing special needs to be done to find bus 0 */
 141         /* Allow the HT devices to be found */
 142         enumerate_ht_chain();
 143
 144         sio_setup();
 145
 146         /* Setup the ck804 */
 147         ck804_enable_rom();
 148
 149         /* Is this a deliberate reset by the BIOS? */
 150         if (bios_reset_detected() && last_boot_normal_x) {
 151                 goto normal_image;
 152         }
 153
 154         /* This is the primary CPU. How should I boot? */
 155         else if (do_normal_boot()) {
 156                 goto normal_image;
 157         } else {
 158                 goto fallback_image;
 159         }
 160
 161 normal_image:
 162         __asm__ volatile ("jmp __normal_image"
 163                 :                                       /* outputs */
 164                 :"a" (bist), "b"(cpu_init_detectedx)    /* inputs */
 165                 );
 166
 167 fallback_image:
 168
 169 #if CONFIG_HAVE_FAILOVER_BOOT == 1
 170         __asm__ volatile ("jmp __fallback_image"
 171                 :                                       /* outputs */
 172                 :"a" (bist), "b"(cpu_init_detectedx)    /* inputs */
 173                 )
 174 #endif
 175         ;
 176 }
 177
 178 #endif /* ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) ... */
 179
 180 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 181
 182 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 183 {
 184 #if CONFIG_HAVE_FAILOVER_BOOT == 1
 185 #if CONFIG_USE_FAILOVER_IMAGE == 1
 186         failover_process(bist, cpu_init_detectedx);
 187 #else
 188         real_main(bist, cpu_init_detectedx);
 189 #endif
 190 #else
 191 #if CONFIG_USE_FALLBACK_IMAGE == 1
 192         failover_process(bist, cpu_init_detectedx);
 193 #endif
 194         real_main(bist, cpu_init_detectedx);
 195 #endif
 196 }
 197
 198 #if CONFIG_USE_FAILOVER_IMAGE == 0
 199 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 200 {
 201         static const uint16_t spd_addr[] = {
 202                 (0xa << 3) | 0, (0xa << 3) | 1, 0, 0,
 203                 0, 0, 0, 0,
 204                 0, 0, 0, 0,
 205                 0, 0, 0, 0,
 206         };
 207
 208         int needs_reset;
 209         unsigned bsp_apicid = 0;
 210
 211         struct mem_controller ctrl[8];
 212         unsigned nodes;
 213
 214         if (bist == 0) {
 215                 bsp_apicid = init_cpus(cpu_init_detectedx);
 216         }
 217
 218         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 219         uart_init();
 220         console_init();
 221
 222         /* Halt if there was a built in self test failure */
 223         report_bist_failure(bist);
 224
 225 #if 0
 226         dump_pci_device(PCI_DEV(0, 0x18, 0));
 227 #endif
 228
 229         needs_reset = setup_coherent_ht_domain();
 230
 231         wait_all_core0_started();
 232 #if CONFIG_LOGICAL_CPUS==1
 233         // It is said that we should start core1 after all core0 launched
 234         start_other_cores();
 235         wait_all_other_cores_started(bsp_apicid);
 236 #endif
 237
 238         needs_reset |= ht_setup_chains_x();
 239
 240         needs_reset |= ck804_early_setup_x();
 241
 242         if (needs_reset) {
 243                 print_info("ht reset -\r\n");
 244                 soft_reset();
 245         }
 246
 247         allow_all_aps_stop(bsp_apicid);
 248
 249         nodes = get_nodes();
 250         //It's the time to set ctrl now;
 251         fill_mem_ctrl(nodes, ctrl, spd_addr);
 252
 253         enable_smbus();
 254
 255 #if 0
 256         dump_spd_registers(&ctrl[0]);
 257         dump_smbus_registers();
 258 #endif
 259
 260         memreset_setup();
 261         sdram_initialize(nodes, ctrl);
 262
 263 #if 0
 264         print_pci_devices();
 265         dump_pci_devices();
 266 #endif
 267
 268         post_cache_as_ram();
 269 }
 270 #endif /* CONFIG_USE_FAILOVER_IMAGE */