2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 AMD
5 * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
6 * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
7 * (Thanks to LSRA University of Mannheim for their support)
8 * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
25 #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
29 #include <device/pci_def.h>
31 #include <device/pnp_def.h>
32 #include <arch/romcc_io.h>
33 #include <cpu/x86/lapic.h>
34 #include <pc80/mc146818rtc.h>
35 #include "cpu/x86/lapic/boot_cpu.c"
36 #include "northbridge/amd/amdk8/reset_test.c"
37 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
39 #include <cpu/amd/model_fxx_rev.h>
40 #include <console/console.h>
41 #include "northbridge/amd/amdk8/incoherent_ht.c"
42 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
43 #include "northbridge/amd/amdk8/raminit.h"
44 #include "cpu/amd/model_fxx/apic_timer.c"
45 #include "lib/delay.c"
46 #include "northbridge/amd/amdk8/debug.c"
47 #include "cpu/x86/mtrr/earlymtrr.c"
48 #include "cpu/x86/bist.h"
49 #include "northbridge/amd/amdk8/setup_resource_map.c"
50 #include "northbridge/amd/amdk8/coherent_ht.c"
51 #include "cpu/amd/dualcore/dualcore.c"
54 static void memreset(int controllers, const struct mem_controller *ctrl)
56 /* FIXME: Nothing to do? */
59 static inline void activate_spd_rom(const struct mem_controller *ctrl)
61 /* FIXME: Nothing to do? */
64 static inline int spd_read_byte(unsigned device, unsigned address)
66 return smbus_read_byte(device, address);
69 #include "northbridge/amd/amdk8/raminit.c"
70 #include "lib/generic_sdram.c"
71 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
72 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
74 #include "cpu/amd/car/post_cache_as_ram.c"
75 #include "cpu/amd/model_fxx/init_cpus.c"
77 #include "northbridge/amd/amdk8/early_ht.c"
79 static void sio_setup(void)
84 /* Subject decoding */
85 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
87 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
89 /* LPC Positive Decode 0 */
90 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
91 /* Serial 0, Serial 1 */
92 dword |= (1 << 0) | (1 << 1);
93 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
96 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
98 static const uint16_t spd_addr[] = {
106 unsigned bsp_apicid = 0;
108 struct mem_controller ctrl[8];
111 if (!cpu_init_detectedx && boot_cpu()) {
112 /* Nothing special needs to be done to find bus 0 */
113 /* Allow the HT devices to be found */
114 enumerate_ht_chain();
120 bsp_apicid = init_cpus(cpu_init_detectedx);
123 w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
127 /* Halt if there was a built in self test failure */
128 report_bist_failure(bist);
131 dump_pci_device(PCI_DEV(0, 0x18, 0));
134 needs_reset = setup_coherent_ht_domain();
136 wait_all_core0_started();
137 #if CONFIG_LOGICAL_CPUS==1
138 // It is said that we should start core1 after all core0 launched
140 wait_all_other_cores_started(bsp_apicid);
143 needs_reset |= ht_setup_chains_x();
145 needs_reset |= ck804_early_setup_x();
148 print_info("ht reset -\n");
152 allow_all_aps_stop(bsp_apicid);
155 //It's the time to set ctrl now;
156 fill_mem_ctrl(nodes, ctrl, spd_addr);
161 dump_spd_registers(&ctrl[0]);
162 dump_smbus_registers();
165 sdram_initialize(nodes, ctrl);