2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Mats Erik Andersson <mats.andersson@gisladisker.org>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 default ROM_SECTION_SIZE = FALLBACK_SIZE
23 default ROM_SECTION_OFFSET = (ROM_SIZE - FALLBACK_SIZE)
25 default ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
26 default ROM_SECTION_OFFSET = 0
29 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
30 default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
32 default _ROMBASE = (CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE)
34 default XIP_ROM_SIZE = 64 * 1024
35 default XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
45 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
46 action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
48 makerule ./failover.inc
49 depends "$(MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
50 action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
53 # depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
54 depends "$(MAINBOARD)/auto.c ../romcc"
55 action "../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
58 # depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
59 depends "$(MAINBOARD)/auto.c ../romcc"
60 action "../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
63 mainboardinit cpu/x86/16bit/entry16.inc
64 mainboardinit cpu/x86/32bit/entry32.inc
65 ldscript /cpu/x86/16bit/entry16.lds
66 ldscript /cpu/x86/32bit/entry32.lds
69 mainboardinit cpu/x86/16bit/reset16.inc
70 ldscript /cpu/x86/16bit/reset16.lds
72 mainboardinit cpu/x86/32bit/reset32.inc
73 ldscript /cpu/x86/32bit/reset32.lds
76 mainboardinit arch/i386/lib/cpu_reset.inc
78 mainboardinit arch/i386/lib/id.inc
79 ldscript /arch/i386/lib/id.lds
82 ldscript /arch/i386/lib/failover.lds
83 mainboardinit ./failover.inc
86 mainboardinit cpu/x86/fpu/enable_fpu.inc
87 mainboardinit cpu/x86/mmx/enable_mmx.inc
88 mainboardinit ./auto.inc
89 mainboardinit cpu/x86/mmx/disable_mmx.inc
94 chip northbridge/intel/i440bx # Northbridge
95 device apic_cluster 0 on # APIC cluster
96 chip cpu/intel/slot_2 # CPU (FIXME: It's slot 1, actually)
97 device apic 0 on end # APIC
100 device pci_domain 0 on # PCI domain
101 device pci 0.0 on end # Host bridge
102 device pci 1.0 on end # PCI/AGP bridge
103 chip southbridge/intel/i82371eb # Southbridge
104 device pci 7.0 on # ISA bridge
105 chip superio/winbond/w83977tf # Super I/O
106 device pnp 3f0.0 on # Floppy
111 device pnp 3f0.1 on # Parallel port
116 device pnp 3f0.2 on # COM1
120 device pnp 3f0.3 on # COM2 / IR
124 device pnp 3f0.5 on # PS/2 keyboard
127 irq 0x70 = 1 # PS/2 keyboard interrupt
128 irq 0x72 = 12 # PS/2 mouse interrupt
130 device pnp 3f0.7 on # GPIO 1
132 device pnp 3f0.8 on # GPIO 2
134 device pnp 3f0.9 off # GPIO 3
136 device pnp 3f0.a on # ACPI
140 device pci 7.1 on end # IDE
141 device pci 7.2 on end # USB
142 device pci 7.3 on end # ACPI
143 register "ide0_enable" = "1"
144 register "ide1_enable" = "1"
145 register "ide_legacy_enable" = "1"
146 # Enable UDMA/33 for higher speed if your IDE device(s) support it.
147 register "ide0_drive0_udma33_enable" = "1"
148 register "ide0_drive1_udma33_enable" = "1"
149 register "ide1_drive0_udma33_enable" = "1"
150 register "ide1_drive1_udma33_enable" = "1"