2 uses CONFIG_ISA_IO_BASE
4 uses CONFIG_ISA_MEM_BASE
5 uses CONFIG_PCIC0_CFGADDR
6 uses CONFIG_PCIC0_CFGDATA
7 uses CONFIG_PNP_CFGADDR
8 uses CONFIG_PNP_CFGDATA
11 uses CONFIG_CROSS_COMPILE
12 uses CONFIG_HAVE_OPTION_TABLE
13 uses CONFIG_SANDPOINT_ALTIMUS
15 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
17 uses CONFIG_CHIP_CONFIGURE
19 uses CONFIG_CONSOLE_SERIAL8250
20 uses CONFIG_TTYS0_BASE
22 uses CONFIG_FS_PAYLOAD
24 uses CONFIG_FS_ISO9660
26 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
27 uses CONFIG_PRECOMPRESSED_PAYLOAD
28 uses CONFIG_AUTOBOOT_CMDLINE
29 uses CONFIG_PAYLOAD_SIZE
31 uses CONFIG_ROM_IMAGE_SIZE
33 uses CONFIG_EXCEPTION_VECTORS
38 uses CONFIG_STACK_SIZE
42 uses CONFIG_MAINBOARD_VENDOR
43 uses CONFIG_MAINBOARD_PART_NUMBER
44 uses COREBOOT_EXTRA_VERSION
45 uses CONFIG_CROSS_COMPILE
53 default CONFIG_ISA_IO_BASE=0xfe000000
54 default CONFIG_ISA_MEM_BASE=0xfd000000
55 default CONFIG_PCIC0_CFGADDR=0xfec00000
56 default CONFIG_PCIC0_CFGDATA=0xfee00000
57 default CONFIG_PNP_CFGADDR=0x15c
58 default CONFIG_PNP_CFGDATA=0x15d
59 default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE
62 ## The default compiler
64 default CC="$(CONFIG_CROSS_COMPILE)gcc"
66 ## use a cross compiler
67 #default CONFIG_CROSS_COMPILE="powerpc-eabi-"
68 #default CONFIG_CROSS_COMPILE="ppc_74xx-"
69 default CONFIG_ARCH_X86=0
71 ## Use stage 1 initialization code
72 default CONFIG_USE_INIT=1
74 ## Use static configuration
75 default CONFIG_CHIP_CONFIGURE=1
77 ## We don't use compressed image
78 default CONFIG_COMPRESS=0
80 ## Turn off POST codes
81 default CONFIG_NO_POST=1
83 ## Enable serial console
84 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
85 default CONFIG_CONSOLE_SERIAL8250=1
86 default CONFIG_TTYS0_BASE=0x3f8
88 ## Load payload using filo
90 default CONFIG_FS_PAYLOAD=1
91 default CONFIG_FS_EXT2=1
92 default CONFIG_FS_ISO9660=1
93 default CONFIG_FS_FAT=1
94 default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz"
96 # coreboot must fit into 128KB
97 default CONFIG_ROM_IMAGE_SIZE=160*1024
98 default CONFIG_ROM_SIZE=384*1024
99 default CONFIG_PAYLOAD_SIZE=262144
101 # Set stack and heap sizes (stage 2)
102 default CONFIG_STACK_SIZE=0x10000
103 default CONFIG_HEAP_SIZE=0x10000
105 # Sandpoint Demo Board
107 default CONFIG_ROMBASE=0xfff00000
109 ## Sandpoint reset vector
110 default CONFIG_RESET=CONFIG_ROMBASE+0x100
112 ## Exception vectors (other than reset vector)
113 default CONFIG_EXCEPTION_VECTORS=CONFIG_RESET+0x100
115 ## Start of coreboot in the boot rom
116 ## = CONFIG_RESET + exeception vector table size
117 default CONFIG_ROMSTART=CONFIG_RESET+0x3100
119 ## Coreboot C code runs at this location in RAM
120 default CONFIG_RAMBASE=0x00100000
121 default CONFIG_RAMSTART=0x00100000
128 default CONFIG_CBFS=1