2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 ## Based on Options.lb from AMD's DB800 mainboard.
23 uses CONFIG_GENERATE_MP_TABLE
24 uses CONFIG_GENERATE_PIRQ_TABLE
25 uses CONFIG_USE_FALLBACK_IMAGE
26 uses CONFIG_HAVE_FALLBACK_BOOT
27 uses CONFIG_HAVE_HARD_RESET
28 uses CONFIG_HAVE_OPTION_TABLE
29 uses CONFIG_USE_OPTION_TABLE
30 uses CONFIG_ROM_PAYLOAD
31 uses CONFIG_IRQ_SLOT_COUNT
33 uses CONFIG_MAINBOARD_VENDOR
34 uses CONFIG_MAINBOARD_PART_NUMBER
35 uses COREBOOT_EXTRA_VERSION
37 uses CONFIG_FALLBACK_SIZE
38 uses CONFIG_STACK_SIZE
41 uses CONFIG_ROM_SECTION_SIZE
42 uses CONFIG_ROM_IMAGE_SIZE
43 uses CONFIG_ROM_SECTION_SIZE
44 uses CONFIG_ROM_SECTION_OFFSET
46 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
47 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
48 uses CONFIG_PRECOMPRESSED_PAYLOAD
51 uses CONFIG_XIP_ROM_SIZE
52 uses CONFIG_XIP_ROM_BASE
53 uses CONFIG_GENERATE_MP_TABLE
54 uses CONFIG_CROSS_COMPILE
59 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
60 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
61 uses CONFIG_CONSOLE_SERIAL8250
62 uses CONFIG_TTYS0_BAUD
63 uses CONFIG_TTYS0_BASE
65 uses CONFIG_UDELAY_TSC
66 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
67 uses CONFIG_CONSOLE_VGA
68 uses CONFIG_PCI_ROM_RUN
70 uses CONFIG_USE_DCACHE_RAM
71 uses CONFIG_DCACHE_RAM_BASE
72 uses CONFIG_DCACHE_RAM_SIZE
73 uses CONFIG_USE_PRINTK_IN_CAR
74 uses CONFIG_PIRQ_ROUTE
76 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
77 default CONFIG_ROM_SIZE = 512*1024
82 default CONFIG_CONSOLE_VGA = 0
83 default CONFIG_VIDEO_MB = 8
84 default CONFIG_PCI_ROM_RUN = 0
87 ## Build code for the fallback boot
89 default CONFIG_HAVE_FALLBACK_BOOT = 1
94 default CONFIG_GENERATE_MP_TABLE = 0
97 ## Build code to reset the motherboard from coreboot
99 default CONFIG_HAVE_HARD_RESET = 0
101 ## Delay timer options
103 default CONFIG_UDELAY_TSC = 1
104 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
107 ## Build code to export a programmable irq routing table
109 default CONFIG_GENERATE_PIRQ_TABLE = 1
110 default CONFIG_IRQ_SLOT_COUNT = 7
111 default CONFIG_PIRQ_ROUTE = 1
114 ## Build code to export a CMOS option table
116 default CONFIG_HAVE_OPTION_TABLE = 0
119 ### coreboot layout values
122 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
123 default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
124 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
127 ## enable CACHE_AS_RAM specifics
129 default CONFIG_USE_DCACHE_RAM = 1
130 default CONFIG_DCACHE_RAM_BASE = 0xc8000
131 default CONFIG_DCACHE_RAM_SIZE = 0x08000
132 default CONFIG_USE_PRINTK_IN_CAR=1
135 ## Use a small 8K stack
137 default CONFIG_STACK_SIZE = 0x2000
140 ## Use a small 16K heap
142 default CONFIG_HEAP_SIZE = 0x4000
145 ## Only use the option table in a normal image
147 #default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
148 default CONFIG_USE_OPTION_TABLE = 0
150 default CONFIG_RAMBASE = 0x00004000
152 default CONFIG_ROM_PAYLOAD = 1
155 ## The default compiler
157 default CONFIG_CROSS_COMPILE = ""
158 default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
159 default HOSTCC = "gcc"
162 ## The Serial Console
165 # To Enable the Serial Console
166 default CONFIG_CONSOLE_SERIAL8250 = 1
168 ## Select the serial console baud rate
169 default CONFIG_TTYS0_BAUD = 115200
170 #default CONFIG_TTYS0_BAUD = 57600
171 #default CONFIG_TTYS0_BAUD = 38400
172 #default CONFIG_TTYS0_BAUD = 19200
173 #default CONFIG_TTYS0_BAUD = 9600
174 #default CONFIG_TTYS0_BAUD = 4800
175 #default CONFIG_TTYS0_BAUD = 2400
176 #default CONFIG_TTYS0_BAUD = 1200
178 # Select the serial console base port
179 default CONFIG_TTYS0_BASE = 0x3f8
181 # Select the serial protocol
182 # This defaults to 8 data bits, 1 stop bit, and no parity
183 default CONFIG_TTYS0_LCS = 0x3
185 # Compile extra debugging code
186 default CONFIG_DEBUG = 1
189 ### Select the coreboot loglevel
191 ## EMERG 1 system is unusable
192 ## ALERT 2 action must be taken immediately
193 ## CRIT 3 critical conditions
194 ## ERR 4 error conditions
195 ## WARNING 5 warning conditions
196 ## NOTICE 6 normal but significant condition
197 ## INFO 7 informational
198 ## CONFIG_DEBUG 8 debug-level messages
199 ## SPEW 9 Way too many details
201 ## Request this level of debugging output
202 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
203 ## At a maximum only compile in this level of debugging
204 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8