2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 LiPPERT Embedded Computers GmbH
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 ## Based on Options.lb from AMD's DB800 mainboard.
26 uses USE_FALLBACK_IMAGE
27 uses HAVE_FALLBACK_BOOT
29 uses HAVE_OPTION_TABLE
31 uses CONFIG_ROM_PAYLOAD
33 uses CONFIG_FS_PAYLOAD
40 uses MAINBOARD_PART_NUMBER
41 uses COREBOOT_EXTRA_VERSION
50 uses ROM_SECTION_OFFSET
51 uses CONFIG_ROM_PAYLOAD_START
53 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
54 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
55 uses CONFIG_PRECOMPRESSED_PAYLOAD
67 uses DEFAULT_CONSOLE_LOGLEVEL
68 uses MAXIMUM_CONSOLE_LOGLEVEL
69 uses CONFIG_CONSOLE_SERIAL8250
73 uses CONFIG_UDELAY_TSC
74 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
75 uses CONFIG_CONSOLE_VGA
76 uses CONFIG_PCI_ROM_RUN
81 uses CONFIG_USE_PRINTK_IN_CAR
84 ## ROM_SIZE is the size of boot ROM that this board will use.
85 default ROM_SIZE = 512 * 1024
90 default CONFIG_CONSOLE_VGA = 0
91 default CONFIG_VIDEO_MB = 8
92 default CONFIG_PCI_ROM_RUN = 0
95 ## Build code for the fallback boot
97 default HAVE_FALLBACK_BOOT = 1
102 default HAVE_MP_TABLE = 0
105 ## Build code to reset the motherboard from coreboot
107 default HAVE_HARD_RESET = 0
109 ## Delay timer options
111 default CONFIG_UDELAY_TSC = 1
112 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
115 ## Build code to export a programmable irq routing table
117 default HAVE_PIRQ_TABLE = 1
118 default IRQ_SLOT_COUNT = 7
119 default PIRQ_ROUTE = 1
122 ## Build code to export a CMOS option table
124 default HAVE_OPTION_TABLE = 0
127 ### coreboot layout values
130 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
131 default ROM_IMAGE_SIZE = 64 * 1024
132 default FALLBACK_SIZE = 128 * 1024
135 ## enable CACHE_AS_RAM specifics
137 default USE_DCACHE_RAM = 1
138 default DCACHE_RAM_BASE = 0xc8000
139 default DCACHE_RAM_SIZE = 0x08000
140 default CONFIG_USE_PRINTK_IN_CAR=1
143 ## Use a small 8K stack
145 default STACK_SIZE = 8 * 1024
148 ## Use a small 16K heap
150 default HEAP_SIZE = 16 * 1024
153 ## Only use the option table in a normal image
155 #default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
156 default USE_OPTION_TABLE = 0
158 default _RAMBASE = 0x00004000
160 default CONFIG_ROM_PAYLOAD = 1
163 ## The default compiler
165 default CROSS_COMPILE = ""
166 default CC = "$(CROSS_COMPILE)gcc -m32"
167 default HOSTCC = "gcc"
170 ## The Serial Console
173 # To Enable the Serial Console
174 default CONFIG_CONSOLE_SERIAL8250 = 1
176 ## Select the serial console baud rate
177 default TTYS0_BAUD = 115200
178 #default TTYS0_BAUD = 57600
179 #default TTYS0_BAUD = 38400
180 #default TTYS0_BAUD = 19200
181 #default TTYS0_BAUD = 9600
182 #default TTYS0_BAUD = 4800
183 #default TTYS0_BAUD = 2400
184 #default TTYS0_BAUD = 1200
186 # Select the serial console base port
187 default TTYS0_BASE = 0x3f8
189 # Select the serial protocol
190 # This defaults to 8 data bits, 1 stop bit, and no parity
191 default TTYS0_LCS = 0x3
193 # Compile extra debugging code
197 ### Select the coreboot loglevel
199 ## EMERG 1 system is unusable
200 ## ALERT 2 action must be taken immediately
201 ## CRIT 3 critical conditions
202 ## ERR 4 error conditions
203 ## WARNING 5 warning conditions
204 ## NOTICE 6 normal but significant condition
205 ## INFO 7 informational
206 ## DEBUG 8 debug-level messages
207 ## SPEW 9 Way too many details
209 ## Request this level of debugging output
210 default DEFAULT_CONSOLE_LOGLEVEL = 8
211 ## At a maximum only compile in this level of debugging
212 default MAXIMUM_CONSOLE_LOGLEVEL = 8
218 default CONFIG_CBFS=0