src/mainboard/lippert/frontrunner/romstage.c

   1 #include <stdint.h>
   2 #include <spd.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/hlt.h>
   7 #include <console/console.h>
   8 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
   9 #include "cpu/x86/bist.h"
  10 #include "cpu/x86/msr.h"
  11 #include <cpu/amd/gx2def.h>
  12 #include <cpu/amd/geode_post_code.h>
  13 #include "southbridge/amd/cs5535/cs5535.h"
  14
  15 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  16
  17 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
  18 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
  19
  20 #define DIMM0 0xA0
  21 #define DIMM1 0xFF /* DIMM1 is not available/used on this board. */
  22
  23 static const unsigned char spdbytes[] = {       /* 4x Qimonda HYB25DC512160CF-6 */
  24         0xFF, 0xFF,                             /* only values used by raminit.c are set */
  25         [SPD_MEMORY_TYPE]               = SPD_MEMORY_TYPE_SDRAM_DDR,    /* (Fundamental) memory type */
  26         [SPD_NUM_ROWS]                  = 0x0D, /* Number of row address bits [13] */
  27         [SPD_NUM_COLUMNS]               = 0x0A, /* Number of column address bits [10] */
  28         [SPD_NUM_DIMM_BANKS]            = 1,    /* Number of module rows (banks) */
  29         0xFF, 0xFF, 0xFF,
  30         [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x60, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [6.0 ns in BCD] */
  31         0xFF, 0xFF,
  32         [SPD_REFRESH]                   = 0x82, /* Refresh rate/type [Self Refresh, 7.8 us] */
  33         [SPD_PRIMARY_SDRAM_WIDTH]       = 64,   /* SDRAM width (primary SDRAM) [64 bits] */
  34         0xFF, 0xFF, 0xFF,
  35         [SPD_NUM_BANKS_PER_SDRAM]       = 4,    /* SDRAM device attributes, number of banks on SDRAM device */
  36         [SPD_ACCEPTABLE_CAS_LATENCIES]  = 0x1C, /* SDRAM device attributes, CAS latency [3, 2.5, 2] */
  37         0xFF, 0xFF,
  38         [SPD_MODULE_ATTRIBUTES]         = 0x20, /* SDRAM module attributes [differential clk] */
  39         [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, /* SDRAM device attributes, general [Concurrent AP] */
  40         [SPD_SDRAM_CYCLE_TIME_2ND]      = 0x60, /* SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD] */
  41         0xFF,
  42         [SPD_SDRAM_CYCLE_TIME_3RD]      = 0x75, /* SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD] */
  43         0xFF,
  44         [SPD_tRP]                       = 72,   /* Min. row precharge time [18 ns in units of 0.25 ns] */
  45         [SPD_tRRD]                      = 48,   /* Min. row active to row active [12 ns in units of 0.25 ns] */
  46         [SPD_tRCD]                      = 72,   /* Min. RAS to CAS delay [18 ns in units of 0.25 ns] */
  47         [SPD_tRAS]                      = 42,   /* Min. RAS pulse width = active to precharge delay [42 ns] */
  48         [SPD_BANK_DENSITY]              = 0x40, /* Density of each row on module [256 MB] */
  49         0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
  50         [SPD_tRFC]                      = 72    /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [72 ns] */
  51 };
  52
  53 static inline int spd_read_byte(unsigned int device, unsigned int address)
  54 {
  55         if (device != DIMM0)
  56                 return 0xFF;    /* No DIMM1, don't even try. */
  57
  58 #if CONFIG_DEBUG_SMBUS
  59         if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
  60                 print_err("ERROR: spd_read_byte(DIMM0, 0x");
  61                 print_err_hex8(address);
  62                 print_err(") returns 0xff\n");
  63         }
  64 #endif
  65
  66         /* Fake SPD ROM value */
  67         return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;
  68 }
  69
  70 #include "northbridge/amd/gx2/raminit.h"
  71 #include "northbridge/amd/gx2/pll_reset.c"
  72 #include "northbridge/amd/gx2/raminit.c"
  73 #include "lib/generic_sdram.c"
  74 #include "cpu/amd/model_gx2/cpureginit.c"
  75 #include "cpu/amd/model_gx2/syspreinit.c"
  76 #include "cpu/amd/model_lx/msrinit.c"
  77
  78 void main(unsigned long bist)
  79 {
  80         static const struct mem_controller memctrl [] = {
  81                 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
  82         };
  83         unsigned char temp;
  84         SystemPreInit();
  85         msr_init();
  86
  87         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  88         uart_init();
  89         console_init();
  90
  91         cs5535_early_setup();
  92         print_err("done cs5535 early\n");
  93
  94         /* Halt if there was a built in self test failure */
  95         report_bist_failure(bist);
  96
  97         pll_reset();
  98         print_err("done pll_reset\n");
  99
 100         cpuRegInit();
 101         print_err("done cpuRegInit\n");
 102
 103         sdram_initialize(1, memctrl);
 104
 105         print_err("Done sdram_initialize\n");
 106         print_err("Disable watchdog\n");
 107         outb( 0x87, 0x4E);                            //enter SuperIO configuration mode
 108         outb( 0x87, 0x4E);
 109
 110         outb(0x20, 0x4e);
 111         temp = inb(0x4f);
 112         print_debug_hex8(temp);
 113         if (temp != 0x52){
 114                 print_err("CAN NOT READ SUPERIO VID\n");
 115         }
 116
 117         outb(0x29, 0x4e);
 118         outb(0x7c, 0x4f);
 119
 120         outb( 0x07, 0x4E);                            //enable logical device 9
 121         outb( 0x09, 0x4F);
 122         outb(0x30, 0x4e);
 123         outb(1, 0x4f);
 124         outb( 0xF0, 0x4E);                            //set GP33 as outbut in configuration register F0h     Bit4 = \u20180\u2019
 125         outb( 0xC7, 0x4F);
 126         outb( 0xF1, 0x4E);                            //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
 127         temp = inb(0x4F);                            //watchdog function. Make sure to let the other Bits unchanged!
 128         print_debug_hex8(temp);print_debug(":");
 129         temp = temp & ~8;
 130         outb( temp, 0x4F);
 131         temp = inb(0x4F);                            //watchdog function. Make sure to let the other Bits unchanged!
 132         print_debug_hex8(temp);print_debug("\n");
 133         /* Check all of memory */
 134 //      ram_check(0, 16384);
 135         ram_check(0x20000, 0x24000);
 136 //      ram_check(0x00000000, 640*1024);
 137
 138 }
 139