src/mainboard/lippert/frontrunner/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <arch/hlt.h>
  10 #include "pc80/serial.c"
  11 #include "arch/i386/lib/console.c"
  12 #include "lib/ramtest.c"
  13 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  14 #include "cpu/x86/bist.h"
  15 #include "cpu/x86/msr.h"
  16 #include <cpu/amd/gx2def.h>
  17
  18 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  19
  20 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
  21 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
  22 #include "northbridge/amd/gx2/raminit.h"
  23
  24 /* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
  25 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
  26 {
  27         msr_t msr;
  28         /* 1. Initialize GLMC registers base on SPD values,
  29          * Hard coded as XpressROM for now */
  30         //print_debug("sdram_enable step 1\r\n");
  31         msr = rdmsr(0x20000018);
  32         msr.hi = 0x10076013;
  33         msr.lo = 0x3400;
  34         wrmsr(0x20000018, msr);
  35
  36         msr = rdmsr(0x20000019);
  37         msr.hi = 0x18000008;
  38         msr.lo = 0x696332a3;
  39         wrmsr(0x20000019, msr);
  40
  41 }
  42
  43 #include "northbridge/amd/gx2/raminit.c"
  44 #include "lib/generic_sdram.c"
  45
  46 #define PLLMSRhi 0x00000226
  47 #define PLLMSRlo 0x00000008
  48 #define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
  49 #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
  50 #include "northbridge/amd/gx2/pll_reset.c"
  51 #include "cpu/amd/model_gx2/cpureginit.c"
  52 #include "cpu/amd/model_gx2/syspreinit.c"
  53 static void msr_init(void)
  54 {
  55         __builtin_wrmsr(0x1808,  0x10f3bf00, 0x22fffc02);
  56
  57         __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
  58         __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
  59         __builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
  60         __builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
  61         __builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
  62         __builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
  63
  64         __builtin_wrmsr(0x10000080, 0x3, 0x0);
  65
  66         __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
  67         __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000);
  68         __builtin_wrmsr(0x40000023, 0x400fffc0, 0x20000040);
  69         __builtin_wrmsr(0x40000024, 0xff4ffffc, 0x200000ef);
  70         __builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
  71         __builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
  72
  73
  74         __builtin_wrmsr(0x50002001, 0x27, 0x0);
  75         __builtin_wrmsr(0x4c002001, 0x1, 0x0);
  76 }
  77
  78
  79 static void main(unsigned long bist)
  80 {
  81         static const struct mem_controller memctrl [] = {
  82                 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
  83         };
  84         unsigned char temp;
  85         SystemPreInit();
  86         msr_init();
  87
  88         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  89         uart_init();
  90         console_init();
  91
  92         cs5535_early_setup();
  93         print_err("done cs5535 early\n");
  94         pll_reset();
  95         print_err("done pll_reset\n");
  96
  97         cpuRegInit();
  98         print_err("done cpuRegInit\n");
  99
 100         sdram_initialize(1, memctrl);
 101
 102         print_err("Done sdram_initialize\n");
 103         print_err("Disable watchdog\n");
 104         outb( 0x87, 0x4E);                            //enter SuperIO configuration mode
 105         outb( 0x87, 0x4E);
 106
 107
 108         outb(0x20, 0x4e);
 109         temp = inb(0x4f);
 110         print_debug_hex8(temp);
 111         if (temp != 0x52){
 112                 print_err("CAN NOT READ SUPERIO VID\n");
 113         }
 114
 115         outb(0x29, 0x4e);
 116         outb(0x7c, 0x4f);
 117
 118         outb( 0x07, 0x4E);                            //enable logical device 9
 119         outb( 0x09, 0x4F);
 120         outb(0x30, 0x4e);
 121         outb(1, 0x4f);
 122         outb( 0xF0, 0x4E);                            //set GP33 as outbut in configuration register F0h     Bit4 = \u20180\u2019
 123         outb( 0xC7, 0x4F);
 124         outb( 0xF1, 0x4E);                            //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
 125         temp = inb(0x4F);                            //watchdog function. Make sure to let the other Bits unchanged!
 126         print_debug_hex8(temp);print_debug(":");
 127         temp = temp & ~8;
 128         outb( temp, 0x4F);
 129         temp = inb(0x4F);                            //watchdog function. Make sure to let the other Bits unchanged!
 130         print_debug_hex8(temp);print_debug("\n");
 131         /* Check all of memory */
 132 //      ram_check(0, 16384);
 133         ram_check(0x20000, 0x24000);
 134 //      ram_check(0x00000000, 640*1024);
 135
 136 }