2 #include <device/pci_def.h>
4 #include <device/pnp_def.h>
6 #include <console/console.h>
7 #include "lib/ramtest.c"
8 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
9 #include "cpu/x86/bist.h"
10 #include "cpu/x86/msr.h"
11 #include <cpu/amd/gx2def.h>
12 #include <cpu/amd/geode_post_code.h>
13 #include "southbridge/amd/cs5535/cs5535.h"
15 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
17 #include "southbridge/amd/cs5535/cs5535_early_smbus.c"
18 #include "southbridge/amd/cs5535/cs5535_early_setup.c"
19 #include "northbridge/amd/gx2/raminit.h"
21 /* this has to be done on a per-mainboard basis, esp. if you don't have smbus */
22 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
25 /* 1. Initialize GLMC registers base on SPD values,
26 * Hard coded as XpressROM for now */
27 //print_debug("sdram_enable step 1\n");
28 msr = rdmsr(0x20000018);
31 wrmsr(0x20000018, msr);
33 msr = rdmsr(0x20000019);
36 wrmsr(0x20000019, msr);
40 #include "northbridge/amd/gx2/raminit.c"
41 #include "lib/generic_sdram.c"
43 #define PLLMSRhi 0x00000226
44 #define PLLMSRlo 0x00000008
45 #define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
46 #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
47 #include "northbridge/amd/gx2/pll_reset.c"
48 #include "cpu/amd/model_gx2/cpureginit.c"
49 #include "cpu/amd/model_gx2/syspreinit.c"
50 #include "cpu/amd/model_lx/msrinit.c"
52 void main(unsigned long bist)
54 static const struct mem_controller memctrl [] = {
55 {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
61 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
66 print_err("done cs5535 early\n");
68 /* Halt if there was a built in self test failure */
69 report_bist_failure(bist);
72 print_err("done pll_reset\n");
75 print_err("done cpuRegInit\n");
77 sdram_initialize(1, memctrl);
79 print_err("Done sdram_initialize\n");
80 print_err("Disable watchdog\n");
81 outb( 0x87, 0x4E); //enter SuperIO configuration mode
86 print_debug_hex8(temp);
88 print_err("CAN NOT READ SUPERIO VID\n");
94 outb( 0x07, 0x4E); //enable logical device 9
98 outb( 0xF0, 0x4E); //set GP33 as outbut in configuration register F0h Bit4 = \u20180\u2019
100 outb( 0xF1, 0x4E); //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
101 temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
102 print_debug_hex8(temp);print_debug(":");
105 temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
106 print_debug_hex8(temp);print_debug("\n");
107 /* Check all of memory */
108 // ram_check(0, 16384);
109 ram_check(0x20000, 0x24000);
110 // ram_check(0x00000000, 640*1024);