2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <console/console.h>
24 #include <device/device.h>
26 #include <boot/tables.h>
28 #include <arch/coreboot_tables.h>
30 #include <device/pci_def.h>
31 #include <device/pci_ops.h>
33 #include <ec/lenovo/pmh7/pmh7.h>
34 #include <ec/acpi/ec.h>
35 #include <ec/lenovo/h8/h8.h>
36 #include <northbridge/intel/i945/i945.h>
37 #include <pc80/mc146818rtc.h>
39 #include <arch/x86/include/arch/acpigen.h>
41 static struct cst_entry cst_entries[] = {
42 { 0x7f, 1, 2, 0, 1, 1, 1, 1000 },
43 { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV2, 2, 1, 500 },
44 { 0x01, 8, 0, 0, DEFAULT_PMBASE + LV3, 2, 17, 250 },
47 int get_cst_entries(struct cst_entry **entries)
49 *entries = cst_entries;
50 return ARRAY_SIZE(cst_entries);
53 static void mainboard_enable(device_t dev)
55 device_t dev0, idedev;
56 u8 defaults_loaded = 0;
60 if (inb(0x164c) & 0x08) {
64 /* If we're resuming from suspend, blink suspend LED */
65 dev0 = dev_find_slot(0, PCI_DEVFN(0,0));
66 if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)
69 idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
70 if (idedev && idedev->chip_info && dock_ultrabay_device_present()) {
71 struct southbridge_intel_i82801gx_config *config = idedev->chip_info;
72 config->ide_enable_primary = 1;
73 /* enable Ultrabay power */
74 outb(inb(0x1628) | 0x01, 0x1628);
77 /* disable Ultrabay power */
78 outb(inb(0x1628) & ~0x01, 0x1628);
82 if (get_option(&defaults_loaded, "cmos_defaults_loaded") < 0) {
83 printk(BIOS_INFO, "failed to get cmos_defaults_loaded");
87 if (!defaults_loaded) {
88 printk(BIOS_INFO, "Restoring CMOS defaults\n");
89 set_option("tft_brightness", &(u8[]){ 0xff });
90 set_option("volume", &(u8[]){ 0x03 });
91 /* set baudrate to 115200 baud */
92 set_option("baud_rate", &(u8[]){ 0x00 });
93 /* set default debug_level (DEFAULT_CONSOLE_LOGLEVEL starts at 1) */
94 set_option("debug_level", &(u8[]) { CONFIG_DEFAULT_CONSOLE_LOGLEVEL+1 });
95 set_option("cmos_defaults_loaded", &(u8[]){ 0x01 });
99 struct chip_operations mainboard_ops = {
100 CHIP_NAME(CONFIG_MAINBOARD_VENDOR " " CONFIG_MAINBOARD_PART_NUMBER)
101 .enable_dev = mainboard_enable,