src/mainboard/kontron/kt690/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2009 coresystems GmbH
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #if CONFIG_LOGICAL_CPUS==1
  22 #define SET_NB_CFG_54 1
  23 #endif
  24
  25 #define RC0 (6<<8)
  26 #define RC1 (7<<8)
  27
  28 #define DIMM0 0x50
  29 #define DIMM1 0x51
  30
  31 #define SMBUS_HUB 0x71
  32
  33 #include <stdint.h>
  34 #include <string.h>
  35 #include <device/pci_def.h>
  36 #include <arch/io.h>
  37 #include <device/pnp_def.h>
  38 #include <arch/romcc_io.h>
  39 #include <cpu/x86/lapic.h>
  40 #include <pc80/mc146818rtc.h>
  41 #include <console/console.h>
  42
  43 #include <cpu/amd/model_fxx_rev.h>
  44 #include "northbridge/amd/amdk8/raminit.h"
  45 #include "cpu/amd/model_fxx/apic_timer.c"
  46 #include "lib/delay.c"
  47
  48 #include "cpu/x86/lapic/boot_cpu.c"
  49 #include "northbridge/amd/amdk8/reset_test.c"
  50 #include "northbridge/amd/amdk8/debug.c"
  51 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
  52
  53 #include <usbdebug.h>
  54
  55 #include <cpu/amd/mtrr.h>
  56 #include "cpu/x86/bist.h"
  57
  58 #include "northbridge/amd/amdk8/setup_resource_map.c"
  59
  60 #include "southbridge/amd/rs690/rs690_early_setup.c"
  61 #include "southbridge/amd/sb600/sb600_early_setup.c"
  62
  63 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  64 static void memreset(int controllers, const struct mem_controller *ctrl)
  65 {
  66 }
  67
  68 /* called in raminit_f.c */
  69 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  70 {
  71 }
  72
  73 /*called in raminit_f.c */
  74 static inline int spd_read_byte(u32 device, u32 address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 #include "northbridge/amd/amdk8/amdk8.h"
  80 #include "northbridge/amd/amdk8/incoherent_ht.c"
  81 #include "northbridge/amd/amdk8/raminit_f.c"
  82 #include "northbridge/amd/amdk8/coherent_ht.c"
  83 #include "lib/generic_sdram.c"
  84 #include "resourcemap.c"
  85
  86 #include "cpu/amd/dualcore/dualcore.c"
  87
  88
  89 #include "cpu/amd/car/post_cache_as_ram.c"
  90
  91 #include "cpu/amd/model_fxx/init_cpus.c"
  92
  93 #include "cpu/amd/model_fxx/fidvid.c"
  94
  95 #include "northbridge/amd/amdk8/early_ht.c"
  96
  97 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  98 {
  99         device_t dev;
 100         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
 101         int needs_reset = 0;
 102         u32 bsp_apicid = 0;
 103         msr_t msr;
 104         struct cpuid_result cpuid1;
 105         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 106
 107         if (!cpu_init_detectedx && boot_cpu()) {
 108                 /* Nothing special needs to be done to find bus 0 */
 109                 /* Allow the HT devices to be found */
 110                 enumerate_ht_chain();
 111
 112                 /* sb600_lpc_port80(); */
 113                 sb600_pci_port80();
 114         }
 115
 116         if (bist == 0) {
 117                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 118         }
 119
 120         enable_rs690_dev8();
 121         sb600_lpc_init();
 122
 123         dev=PNP_DEV(0x2e, W83627DHG_SP1);
 124         w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE);
 125         uart_init();
 126
 127 #if CONFIG_USBDEBUG
 128         sb600_enable_usbdebug(0);
 129         early_usbdebug_init();
 130 #endif
 131
 132         console_init();
 133
 134         /* Halt if there was a built in self test failure */
 135         report_bist_failure(bist);
 136         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 137
 138         setup_kt690_resource_map();
 139
 140         setup_coherent_ht_domain();
 141
 142 #if CONFIG_LOGICAL_CPUS==1
 143         /* It is said that we should start core1 after all core0 launched */
 144         wait_all_core0_started();
 145         start_other_cores();
 146 #endif
 147         wait_all_aps_started(bsp_apicid);
 148
 149         ht_setup_chains_x(sysinfo);
 150
 151         /* run _early_setup before soft-reset. */
 152         rs690_early_setup();
 153         sb600_early_setup();
 154
 155         /* Check to see if processor is capable of changing FIDVID  */
 156         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 157         cpuid1 = cpuid(0x80000007);
 158         if( (cpuid1.edx & 0x6) == 0x6 ) {
 159
 160                 /* Read FIDVID_STATUS */
 161                 msr=rdmsr(0xc0010042);
 162                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 163
 164                 enable_fid_change();
 165                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 166                 init_fidvid_bsp(bsp_apicid);
 167
 168                 /* show final fid and vid */
 169                 msr=rdmsr(0xc0010042);
 170                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 171
 172         } else {
 173                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 174                 printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
 175         }
 176
 177         needs_reset = optimize_link_coherent_ht();
 178         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 179         rs690_htinit();
 180         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 181
 182         if (needs_reset) {
 183                 print_info("ht reset -\n");
 184                 soft_reset();
 185         }
 186
 187         allow_all_aps_stop(bsp_apicid);
 188
 189         /* It's the time to set ctrl now; */
 190         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 191                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 192         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 193         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 194
 195         rs690_before_pci_init();
 196         sb600_before_pci_init();
 197
 198         post_cache_as_ram();
 199 }
 200