src/mainboard/kontron/kt690/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2009 coresystems GmbH
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  19  */
  20
  21 #define RAMINIT_SYSINFO 1
  22 #define SET_FIDVID 1
  23 #define QRANK_DIMM_SUPPORT 1
  24 #if CONFIG_LOGICAL_CPUS==1
  25 #define SET_NB_CFG_54 1
  26 #endif
  27
  28 #define RC0 (6<<8)
  29 #define RC1 (7<<8)
  30
  31 #define DIMM0 0x50
  32 #define DIMM1 0x51
  33
  34 #define ICS951462_ADDRESS       0x69
  35 #define SMBUS_HUB 0x71
  36
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <device/pci_def.h>
  40 #include <arch/io.h>
  41 #include <device/pnp_def.h>
  42 #include <arch/romcc_io.h>
  43 #include <cpu/x86/lapic.h>
  44 #include <pc80/mc146818rtc.h>
  45 #include <console/console.h>
  46
  47 #include <cpu/amd/model_fxx_rev.h>
  48 #include "northbridge/amd/amdk8/raminit.h"
  49 #include "cpu/amd/model_fxx/apic_timer.c"
  50 #include "lib/delay.c"
  51
  52 #include "cpu/x86/lapic/boot_cpu.c"
  53 #include "northbridge/amd/amdk8/reset_test.c"
  54 #include "northbridge/amd/amdk8/debug.c"
  55 #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
  56
  57 #if CONFIG_USBDEBUG
  58 #include "southbridge/amd/sb600/sb600_enable_usbdebug.c"
  59 #include "pc80/usbdebug_serial.c"
  60 #endif
  61
  62 #include "cpu/x86/mtrr/earlymtrr.c"
  63 #include "cpu/x86/bist.h"
  64
  65 #include "northbridge/amd/amdk8/setup_resource_map.c"
  66
  67 #include "southbridge/amd/rs690/rs690_early_setup.c"
  68 #include "southbridge/amd/sb600/sb600_early_setup.c"
  69
  70 /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
  71 static void memreset(int controllers, const struct mem_controller *ctrl)
  72 {
  73 }
  74
  75 /* called in raminit_f.c */
  76 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  77 {
  78 }
  79
  80 /*called in raminit_f.c */
  81 static inline int spd_read_byte(u32 device, u32 address)
  82 {
  83         return smbus_read_byte(device, address);
  84 }
  85
  86 #include "northbridge/amd/amdk8/amdk8.h"
  87 #include "northbridge/amd/amdk8/incoherent_ht.c"
  88 #include "northbridge/amd/amdk8/raminit_f.c"
  89 #include "northbridge/amd/amdk8/coherent_ht.c"
  90 #include "lib/generic_sdram.c"
  91 #include "resourcemap.c"
  92
  93 #include "cpu/amd/dualcore/dualcore.c"
  94
  95
  96 #include "cpu/amd/car/post_cache_as_ram.c"
  97
  98 #include "cpu/amd/model_fxx/init_cpus.c"
  99
 100 #include "cpu/amd/model_fxx/fidvid.c"
 101
 102 #include "northbridge/amd/amdk8/early_ht.c"
 103
 104 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 105 {
 106         device_t dev;
 107         static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
 108         int needs_reset = 0;
 109         u32 bsp_apicid = 0;
 110         msr_t msr;
 111         struct cpuid_result cpuid1;
 112         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 113
 114         if (!cpu_init_detectedx && boot_cpu()) {
 115                 /* Nothing special needs to be done to find bus 0 */
 116                 /* Allow the HT devices to be found */
 117                 enumerate_ht_chain();
 118
 119                 /* sb600_lpc_port80(); */
 120                 sb600_pci_port80();
 121         }
 122
 123         if (bist == 0) {
 124                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 125         }
 126
 127         enable_rs690_dev8();
 128         sb600_lpc_init();
 129
 130         dev=PNP_DEV(0x2e, W83627DHG_SP1);
 131         w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE);
 132         uart_init();
 133
 134 #if CONFIG_USBDEBUG
 135         sb600_enable_usbdebug(0);
 136         early_usbdebug_init();
 137 #endif
 138
 139         console_init();
 140
 141         /* Halt if there was a built in self test failure */
 142         report_bist_failure(bist);
 143         printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid);
 144
 145         setup_kt690_resource_map();
 146
 147         setup_coherent_ht_domain();
 148
 149 #if CONFIG_LOGICAL_CPUS==1
 150         /* It is said that we should start core1 after all core0 launched */
 151         wait_all_core0_started();
 152         start_other_cores();
 153 #endif
 154         wait_all_aps_started(bsp_apicid);
 155
 156         ht_setup_chains_x(sysinfo);
 157
 158         /* run _early_setup before soft-reset. */
 159         rs690_early_setup();
 160         sb600_early_setup();
 161
 162         /* Check to see if processor is capable of changing FIDVID  */
 163         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 164         cpuid1 = cpuid(0x80000007);
 165         if( (cpuid1.edx & 0x6) == 0x6 ) {
 166
 167                 /* Read FIDVID_STATUS */
 168                 msr=rdmsr(0xc0010042);
 169                 printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 170
 171                 enable_fid_change();
 172                 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 173                 init_fidvid_bsp(bsp_apicid);
 174
 175                 /* show final fid and vid */
 176                 msr=rdmsr(0xc0010042);
 177                 printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
 178
 179         } else {
 180                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 181                 printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
 182         }
 183
 184         needs_reset = optimize_link_coherent_ht();
 185         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 186         rs690_htinit();
 187         printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
 188
 189         if (needs_reset) {
 190                 print_info("ht reset -\n");
 191                 soft_reset();
 192         }
 193
 194         allow_all_aps_stop(bsp_apicid);
 195
 196         /* It's the time to set ctrl now; */
 197         printk(BIOS_DEBUG, "sysinfo->nodes: %2x  sysinfo->ctrl: %p  spd_addr: %p\n",
 198                      sysinfo->nodes, sysinfo->ctrl, spd_addr);
 199         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 200         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 201
 202         rs690_before_pci_init();
 203         sb600_before_pci_init();
 204
 205         post_cache_as_ram();
 206 }
 207