2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2008 Advanced Micro Devices, Inc.
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
15 ## You should have received a copy of the GNU General Public License
16 ## along with this program; if not, write to the Free Software
17 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
23 default CONFIG_XIP_ROM_SIZE = 64 * 1024
24 include /config/nofailovercalculation.lb
29 ## Build the objects we have code for in this directory.
36 if CONFIG_GENERATE_MP_TABLE object mptable.o end
37 if CONFIG_GENERATE_PIRQ_TABLE
42 if CONFIG_GENERATE_ACPI_TABLES
46 depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
47 action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
48 action "mv dsdt.hex dsdt.c"
55 makerule ./cache_as_ram_auto.o
56 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
57 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
62 makerule ./cache_as_ram_auto.inc
63 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
64 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
65 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
66 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
72 ## Build our 16 bit and 32 bit coreboot entry code
74 mainboardinit cpu/x86/16bit/entry16.inc
75 mainboardinit cpu/x86/32bit/entry32.inc
76 ldscript /cpu/x86/16bit/entry16.lds
78 ldscript /cpu/x86/32bit/entry32.lds
82 ldscript /cpu/amd/car/cache_as_ram.lds
86 ## Build our reset vector (This is where coreboot is entered)
88 if CONFIG_USE_FALLBACK_IMAGE
89 mainboardinit cpu/x86/16bit/reset16.inc
90 ldscript /cpu/x86/16bit/reset16.lds
92 mainboardinit cpu/x86/32bit/reset32.inc
93 ldscript /cpu/x86/32bit/reset32.lds
97 ## Include an id string (For safe flashing)
99 mainboardinit arch/i386/lib/id.inc
100 ldscript /arch/i386/lib/id.lds
103 ## Setup Cache-As-Ram
105 mainboardinit cpu/amd/car/cache_as_ram.inc
108 ### This is the early phase of coreboot startup
109 ### Things are delicate and we test to see if we should
110 ### failover to another image.
112 if CONFIG_USE_FALLBACK_IMAGE
113 ldscript /arch/i386/lib/failover.lds
117 ### O.k. We aren't just an intermediary anymore!
124 initobject cache_as_ram_auto.o
126 mainboardinit ./cache_as_ram_auto.inc
130 ## Include the secondary Configuration files
134 #The variables belong to mainboard are defined here.
136 #Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default)
137 #Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
138 #Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
139 # 1: the system allows a PCIE link to be established on Dev2 or Dev3.
140 #Define gfx_dual_slot, 0: single slot, 1: dual slot
141 #Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
142 #Define gfx_tmds, 0: didn't support TMDS, 1: support
143 #Define gfx_compliance, 0: didn't support compliance, 1: support
144 #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
145 #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
146 chip northbridge/amd/amdk8/root_complex
147 device apic_cluster 0 on
148 chip cpu/amd/socket_S1G1
152 device pci_domain 0 on
153 chip northbridge/amd/amdk8
154 device pci 18.0 on # southbridge
155 chip southbridge/amd/rs690
156 device pci 0.0 on end # HT 0x7910
157 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
158 device pci 5.0 on end # Internal Graphics 0x791F
160 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
161 device pci 3.0 off end # PCIE P2P bridge 0x791b
162 device pci 4.0 on end # PCIE P2P bridge 0x7914
163 device pci 5.0 on end # PCIE P2P bridge 0x7915
164 device pci 6.0 on end # PCIE P2P bridge 0x7916
165 device pci 7.0 on end # PCIE P2P bridge 0x7917
166 device pci 8.0 off end # NB/SB Link P2P bridge
167 register "gpp_configuration" = "4"
168 register "port_enable" = "0xfc"
169 register "gfx_dev2_dev3" = "1"
170 register "gfx_dual_slot" = "0"
171 register "gfx_lane_reversal" = "0"
172 register "gfx_tmds" = "0"
173 register "gfx_compliance" = "0"
174 register "gfx_reconfiguration" = "1"
175 register "gfx_link_width" = "0"
177 chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
178 device pci 12.0 on end # SATA 0x4380
179 device pci 13.0 on end # USB 0x4387
180 device pci 13.1 on end # USB 0x4388
181 device pci 13.2 on end # USB 0x4389
182 device pci 13.3 on end # USB 0x438a
183 device pci 13.4 on end # USB 0x438b
184 device pci 13.5 on end # USB 2 0x4386
185 device pci 14.0 on # SM 0x4385
186 chip drivers/generic/generic #dimm 0-0-0
189 chip drivers/generic/generic #dimm 0-0-1
192 chip drivers/generic/generic #dimm 0-1-0
195 chip drivers/generic/generic #dimm 0-1-1
199 device pci 14.1 on end # IDE 0x438c
200 device pci 14.2 on end # HDA 0x4383
201 device pci 14.3 on # LPC 0x438d
202 chip superio/winbond/w83627dhg
203 device pnp 2e.0 off # Floppy
208 device pnp 2e.1 off # Parallel Port
212 device pnp 2e.2 on # Com1
216 device pnp 2e.3 on # Com2
220 device pnp 2e.5 on # Keyboard
225 #device pnp 2e.6 off # SPI
227 device pnp 2e.7 off # GPIO
229 device pnp 2e.8 on # WDTO#, PLED
231 device pnp 2e.9 off # GPIO
233 device pnp 2e.a off # ACPI
235 device pnp 2e.b on # HWM
238 device pnp 2e.c off # PECI, SST
240 end #superio/winbond/w83627dhg
241 #chip superio/smsc/fdc37n972
242 # seems this chip is not used?
245 device pci 14.4 on end # PCI 0x4384
246 device pci 14.5 on end # ACI 0x4382
247 device pci 14.6 on end # MCI 0x438e
248 register "ide0_enable" = "1"
249 register "sata0_enable" = "1"
250 register "hda_viddid" = "0x10ec0888"
251 end #southbridge/amd/sb600
252 end # device pci 18.0
254 device pci 18.0 on end
255 device pci 18.0 on end
256 device pci 18.1 on end
257 device pci 18.2 on end
258 device pci 18.3 on end
259 end #northbridge/amd/amdk8
261 end #northbridge/amd/amdk8/root_complex