2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2008 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 // __ROMCC__ means: use "unsigned" for device, not a struct.
27 #include <arch/romcc_io.h>
28 #include <device/pci_def.h>
29 #include <device/pnp_def.h>
30 #include <cpu/x86/lapic.h>
32 #include "superio/winbond/w83627thg/w83627thg.h"
34 #include "option_table.h"
35 #include "pc80/mc146818rtc_early.c"
37 #include "pc80/serial.c"
38 #include "arch/i386/lib/console.c"
39 #include <cpu/x86/bist.h>
41 #include "ram/ramtest.c"
42 #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c"
44 #include "superio/winbond/w83627thg/w83627thg_early_serial.c"
46 #include "northbridge/intel/i945/udelay.c"
48 #if CONFIG_USE_INIT == 0
49 #include "lib/memcpy.c"
52 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
54 #include "northbridge/intel/i945/ich7.h"
55 static void setup_ich7_gpios(void)
57 /* TODO: This is highly board specific and should be moved */
58 printk_debug(" GPIOS...");
59 /* General Registers */
60 outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
61 outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
62 outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
63 /* Output Control Registers */
64 outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
65 /* Input Control Registers */
66 outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
67 outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
68 outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
69 outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */
72 #include "northbridge/intel/i945/early_init.c"
74 static inline int spd_read_byte(unsigned device, unsigned address)
76 return smbus_read_byte(device, address);
79 /* Usually system firmware turns off system memory clock signals to
80 * unused SO-DIMM slots to reduce EMI and power consumption.
81 * However, the Kontron 986LCD-M does not like unused clock signals to
82 * be disabled. If other similar mainboard occur, it would make sense
83 * to make this an entry in the sysinfo structure, and pre-initialize that
84 * structure in the mainboard's auto.c main() function. For now a
87 #define OVERRIDE_CLOCK_DISABLE 1
88 #include "northbridge/intel/i945/raminit.h"
89 #include "northbridge/intel/i945/raminit.c"
90 #include "northbridge/intel/i945/reset_test.c"
91 #include "northbridge/intel/i945/errata.c"
94 static void ich7_enable_lpc(void)
97 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
98 // Set COM1/COM2 decode range
99 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
100 // Enable COM1/COM2/KBD/SuperIO1+2
101 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b);
102 // Enable HWM at 0xa00
103 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0a01);
105 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9);
107 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9);
109 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301);
113 /* This box has two superios, so enabling serial becomes slightly excessive.
114 * We disable a lot of stuff to make sure that there are no conflicts between
115 * the two. Also set up the GPIOs from the beginning. This is the "no schematic
116 * but safe anyways" method.
118 static void early_superio_config_w83627thg(void)
122 dev=PNP_DEV(0x2e, W83627THG_SP1);
123 pnp_enter_ext_func_mode(dev);
125 pnp_set_logical_device(dev);
126 pnp_set_enable(dev, 0);
127 pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
128 pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
129 pnp_set_enable(dev, 1);
131 dev=PNP_DEV(0x2e, W83627THG_SP2);
132 pnp_set_logical_device(dev);
133 pnp_set_enable(dev, 0);
134 pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
135 pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
136 // pnp_write_config(dev, 0xf1, 4); // IRMODE0
137 pnp_set_enable(dev, 1);
139 dev=PNP_DEV(0x2e, W83627THG_KBC);
140 pnp_set_logical_device(dev);
141 pnp_set_enable(dev, 0);
142 pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
143 pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
144 // pnp_write_config(dev, 0xf0, 0x82);
145 pnp_set_enable(dev, 1);
147 dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1);
148 pnp_set_logical_device(dev);
149 pnp_set_enable(dev, 0);
150 pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs
151 pnp_set_enable(dev, 1);
153 dev=PNP_DEV(0x2e, W83627THG_GPIO2);
154 pnp_set_logical_device(dev);
155 pnp_set_enable(dev, 1); // Just enable it
157 dev=PNP_DEV(0x2e, W83627THG_GPIO3);
158 pnp_set_logical_device(dev);
159 pnp_set_enable(dev, 0);
160 pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
161 pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
162 pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
164 dev=PNP_DEV(0x2e, W83627THG_FDC);
165 pnp_set_logical_device(dev);
166 pnp_set_enable(dev, 0);
168 dev=PNP_DEV(0x2e, W83627THG_PP);
169 pnp_set_logical_device(dev);
170 pnp_set_enable(dev, 0);
172 pnp_exit_ext_func_mode(dev);
174 dev=PNP_DEV(0x4e, W83627THG_SP1);
175 pnp_enter_ext_func_mode(dev);
177 pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values
178 pnp_set_enable(dev, 0);
179 pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8);
180 pnp_set_irq(dev, PNP_IDX_IRQ0, 11);
181 pnp_set_enable(dev, 1);
183 dev=PNP_DEV(0x4e, W83627THG_SP2);
184 pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values
185 pnp_set_enable(dev, 0);
186 pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8);
187 pnp_set_irq(dev, PNP_IDX_IRQ0, 10);
188 pnp_set_enable(dev, 1);
190 dev=PNP_DEV(0x4e, W83627THG_FDC);
191 pnp_set_logical_device(dev);
192 pnp_set_enable(dev, 0);
194 dev=PNP_DEV(0x4e, W83627THG_PP);
195 pnp_set_logical_device(dev);
196 pnp_set_enable(dev, 0);
198 dev=PNP_DEV(0x4e, W83627THG_KBC);
199 pnp_set_logical_device(dev);
200 pnp_set_enable(dev, 0);
201 pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
202 pnp_set_iobase(dev, PNP_IDX_IO1, 0x00);
204 pnp_exit_ext_func_mode(dev);
207 static void rcba_config(void)
209 /* Set up virtual channel 0 */
210 //RCBA32(0x0014) = 0x80000001;
211 //RCBA32(0x001c) = 0x03128010;
213 /* Device 1f interrupt pin register */
214 RCBA32(0x3100) = 0x00042210;
215 /* Device 1d interrupt pin register */
216 RCBA32(0x310c) = 0x00214321;
218 /* dev irq route register */
219 RCBA16(0x3140) = 0x0132;
220 RCBA16(0x3142) = 0x3241;
221 RCBA16(0x3144) = 0x0237;
222 RCBA16(0x3146) = 0x3210;
223 RCBA16(0x3148) = 0x3210;
226 RCBA8(0x31ff) = 0x03;
228 /* Enable upper 128bytes of CMOS */
229 RCBA32(0x3400) = (1 << 2);
231 /* Disable unused devices */
232 RCBA32(0x3418) = 0x000e0063;
234 /* Enable PCIe Root Port Clock Gate */
235 // RCBA32(0x341c) = 0x00000001;
238 static void early_ich7_init(void)
243 // program secondary mlt XXX byte?
244 pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
246 // reset rtc power status
247 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
249 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
251 // usb transient disconnect
252 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
254 pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
256 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
257 reg32 |= (1 << 29) | (1 << 17);
258 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
260 reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
261 reg32 |= (1 << 31) | (1 << 27);
262 pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
264 RCBA32(0x0088) = 0x0011d000;
265 RCBA16(0x01fc) = 0x060f;
266 RCBA32(0x01f4) = 0x86000040;
267 RCBA32(0x0214) = 0x10030549;
268 RCBA32(0x0218) = 0x00020504;
269 RCBA8(0x0220) = 0xc5;
270 reg32 = RCBA32(0x3410);
272 RCBA32(0x3410) = reg32;
273 reg32 = RCBA32(0x3430);
276 RCBA32(0x3430) = reg32;
277 RCBA32(0x3418) |= (1 << 0);
278 RCBA16(0x0200) = 0x2008;
279 RCBA8(0x2027) = 0x0d;
280 RCBA16(0x3e08) |= (1 << 7);
281 RCBA16(0x3e48) |= (1 << 7);
282 RCBA32(0x3e0e) |= (1 << 7);
283 RCBA32(0x3e4e) |= (1 << 7);
285 // next step only on ich7m b0 and later:
286 reg32 = RCBA32(0x2034);
287 reg32 &= ~(0x0f << 16);
289 RCBA32(0x2034) = reg32;
292 #if USE_FALLBACK_IMAGE == 1
293 #include "southbridge/intel/i82801gx/cmos_failover.c"
296 void real_main(unsigned long bist)
305 early_superio_config_w83627thg();
307 /* Set up the console */
311 /* Halt if there was a built in self test failure */
312 report_bist_failure(bist);
314 if (MCHBAR16(SSKPD) == 0xCAFE) {
315 printk_debug("soft reset detected.\n");
319 /* Perform some early chipset initialization required
320 * before RAM initialization can work
322 i945_early_initialization();
324 /* Enable SPD ROMs and DDR-II DRAM */
327 #if DEFAULT_CONSOLE_LOGLEVEL > 8
328 dump_spd_registers();
331 sdram_initialize(boot_mode);
333 /* Perform some initialization that must run before stage2 */
336 /* This should probably go away. Until now it is required
337 * and mainboard specific
341 /* Chipset Errata! */
344 /* Initialize the internal PCIe links before we go into stage2 */
345 i945_late_initialization();
347 #if DEFAULT_CONSOLE_LOGLEVEL > 8
348 #if defined(DEBUG_RAM_SETUP)
349 sdram_dump_mchbar_registers();
353 /* This will not work if TSEG is in place! */
354 u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c);
356 printk_debug("TOM: 0x%08x\n", tom);
357 ram_check(0x00000000, 0x000a0000);
358 ram_check(0x00100000, tom);
361 MCHBAR16(SSKPD) = 0xCAFE;
364 #include "cpu/intel/model_6ex/cache_as_ram_disable.c"