2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2008 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 uses HAVE_OPTION_TABLE
28 uses LB_CKS_RANGE_START
33 uses HAVE_MAINBOARD_RESOURCES
37 uses CONFIG_LOGICAL_CPUS
38 uses CONFIG_AP_IN_SIPI_WAIT
40 uses CONFIG_MAX_PHYSICAL_CPUS
43 uses USE_FALLBACK_IMAGE
44 uses HAVE_FALLBACK_BOOT
50 uses ROM_SECTION_OFFSET
52 uses CONFIG_ROM_PAYLOAD
53 uses CONFIG_ROM_PAYLOAD_START
54 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
55 uses CONFIG_PRECOMPRESSED_PAYLOAD
66 uses CONFIG_USE_PRINTK_IN_CAR
71 uses CONFIG_PCIE_CONFIGSPACE_HOLE
73 uses MMCONF_BASE_ADDRESS
79 uses MAINBOARD_PART_NUMBER
81 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
82 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
84 uses CONFIG_UDELAY_TSC
85 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
87 uses CONFIG_CONSOLE_SERIAL8250
91 uses DEFAULT_CONSOLE_LOGLEVEL
92 uses MAXIMUM_CONSOLE_LOGLEVEL
93 uses CONFIG_CONSOLE_VGA
94 uses CONFIG_VGA_ROM_RUN
95 uses CONFIG_PCI_ROM_RUN
105 uses USE_WATCHDOG_ON_BOOT
106 uses COREBOOT_EXTRA_VERSION
107 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
115 default MAX_REBOOT_CNT=3
118 ## Use the watchdog to break out of a lockup condition
120 default USE_WATCHDOG_ON_BOOT=0
123 ## ROM_SIZE is the size of boot ROM that this board will use.
125 default ROM_SIZE=1024*1024
129 ## Build code for the fallback boot
131 default HAVE_FALLBACK_BOOT=1
134 ## Delay timer options
137 default CONFIG_UDELAY_TSC=1
138 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
141 ## Build code to reset the motherboard from coreboot
143 default HAVE_HARD_RESET=1
148 default HAVE_SMI_HANDLER=1
151 ## Leave a hole for mmapped PCIe config space
154 default CONFIG_PCIE_CONFIGSPACE_HOLE=1
155 default MMCONF_SUPPORT=1
156 default MMCONF_BASE_ADDRESS=0xf0000000
161 default CONFIG_GFXUMA=1
164 ## Build code to export a programmable irq routing table
166 default HAVE_PIRQ_TABLE=1
167 default IRQ_SLOT_COUNT=18
170 ## Build code to export an x86 MP table
171 ## Useful for specifying IRQ routing values
173 default HAVE_MP_TABLE=1
176 ## Build code to provide ACPI support
178 default HAVE_ACPI_TABLES=1
179 default HAVE_MAINBOARD_RESOURCES=1
180 default HAVE_HIGH_TABLES=1
183 ## Build code to export a CMOS option table
185 default HAVE_OPTION_TABLE=1
188 ## Move the default coreboot cmos range off of AMD RTC registers
190 default LB_CKS_RANGE_START=49
191 default LB_CKS_RANGE_END=122
192 default LB_CKS_LOC=123
195 default CONFIG_CONSOLE_VGA=1
196 # There are some network option roms that don't work with
197 # coreboot's x86emu. Thus, we only execute the VGA option rom
199 default CONFIG_VGA_ROM_RUN=1
200 default CONFIG_PCI_ROM_RUN=0
204 ## Build code for SMP support
205 ## Only worry about 2 micro processors
208 default CONFIG_MAX_CPUS=4
209 default CONFIG_MAX_PHYSICAL_CPUS=2
210 default CONFIG_LOGICAL_CPUS=1
211 default CONFIG_AP_IN_SIPI_WAIT=1
214 ## enable CACHE_AS_RAM specifics
216 default USE_DCACHE_RAM=1
217 default DCACHE_RAM_SIZE=0x8000
218 default DCACHE_RAM_BASE=( 0xfff00000 - DCACHE_RAM_SIZE - 1024*1024)
219 default CONFIG_USE_PRINTK_IN_CAR=1
222 ## Build code to setup a generic IOAPIC
224 default CONFIG_IOAPIC=1
227 ## Clean up the motherboard id strings
229 default MAINBOARD_PART_NUMBER="986LCD-M"
230 default MAINBOARD_VENDOR= "KONTRON"
233 ### coreboot layout values
236 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
237 default ROM_IMAGE_SIZE = 65536
240 ## Use a small 8K stack
242 default STACK_SIZE=0x2000
245 ## Use a small 32K heap
247 default HEAP_SIZE=0x8000
251 ### Compute the location and size of where this firmware image
252 ### (coreboot plus bootloader) will live in the boot rom chip.
254 default FALLBACK_SIZE=131072
257 ## coreboot C code runs at this location in RAM
259 default _RAMBASE=0x00100000
262 ## Load the payload from the ROM
264 default CONFIG_ROM_PAYLOAD=1
267 ### Defaults of options that you may want to override in the target config file
271 ## The default compiler
273 default CC="$(CROSS_COMPILE)gcc -m32"
277 ## Disable the gdb stub by default
279 default CONFIG_GDB_STUB=0
282 ## The Serial Console
285 # To Enable the Serial Console
286 default CONFIG_CONSOLE_SERIAL8250=1
288 ## Select the serial console baud rate
289 default TTYS0_BAUD=115200
290 #default TTYS0_BAUD=57600
291 #default TTYS0_BAUD=38400
292 #default TTYS0_BAUD=19200
293 #default TTYS0_BAUD=9600
294 #default TTYS0_BAUD=4800
295 #default TTYS0_BAUD=2400
296 #default TTYS0_BAUD=1200
298 # Select the serial console base port
299 default TTYS0_BASE=0x3f8
301 # Select the serial protocol
302 # This defaults to 8 data bits, 1 stop bit, and no parity
303 default TTYS0_LCS=0x3
306 ### Select the coreboot loglevel
308 ## EMERG 1 system is unusable
309 ## ALERT 2 action must be taken immediately
310 ## CRIT 3 critical conditions
311 ## ERR 4 error conditions
312 ## WARNING 5 warning conditions
313 ## NOTICE 6 normal but significant condition
314 ## INFO 7 informational
315 ## DEBUG 8 debug-level messages
316 ## SPEW 9 Way too many details
318 ## Request this level of debugging output
319 default DEFAULT_CONSOLE_LOGLEVEL=5
320 ## At a maximum only compile in this level of debugging
321 default MAXIMUM_CONSOLE_LOGLEVEL=9
324 ## Select power on after power fail setting
325 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
330 default CONFIG_ROMFS=0