2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2008 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
26 uses HAVE_OPTION_TABLE
28 uses LB_CKS_RANGE_START
33 uses HAVE_MAINBOARD_RESOURCES
36 uses CONFIG_LOGICAL_CPUS
37 uses CONFIG_AP_IN_SIPI_WAIT
39 uses CONFIG_MAX_PHYSICAL_CPUS
42 uses USE_FALLBACK_IMAGE
43 uses HAVE_FALLBACK_BOOT
49 uses ROM_SECTION_OFFSET
51 uses CONFIG_ROM_PAYLOAD
52 uses CONFIG_ROM_PAYLOAD_START
53 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
54 uses CONFIG_PRECOMPRESSED_PAYLOAD
65 uses CONFIG_USE_PRINTK_IN_CAR
70 uses CONFIG_PCIE_CONFIGSPACE_HOLE
72 uses MMCONF_BASE_ADDRESS
78 uses MAINBOARD_PART_NUMBER
80 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
81 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
83 uses CONFIG_UDELAY_TSC
84 uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
86 uses CONFIG_CONSOLE_SERIAL8250
90 uses DEFAULT_CONSOLE_LOGLEVEL
91 uses MAXIMUM_CONSOLE_LOGLEVEL
92 uses CONFIG_CONSOLE_VGA
93 uses CONFIG_VGA_ROM_RUN
94 uses CONFIG_PCI_ROM_RUN
104 uses USE_WATCHDOG_ON_BOOT
105 uses COREBOOT_EXTRA_VERSION
106 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
114 default MAX_REBOOT_CNT=3
117 ## Use the watchdog to break out of a lockup condition
119 default USE_WATCHDOG_ON_BOOT=0
122 ## ROM_SIZE is the size of boot ROM that this board will use.
124 default ROM_SIZE=1024*1024
128 ## Build code for the fallback boot
130 default HAVE_FALLBACK_BOOT=1
133 ## Delay timer options
136 default CONFIG_UDELAY_TSC=1
137 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
140 ## Build code to reset the motherboard from coreboot
142 default HAVE_HARD_RESET=1
147 default HAVE_SMI_HANDLER=1
150 ## Leave a hole for mmapped PCIe config space
153 default CONFIG_PCIE_CONFIGSPACE_HOLE=1
154 default MMCONF_SUPPORT=1
155 default MMCONF_BASE_ADDRESS=0xf0000000
160 default CONFIG_GFXUMA=1
163 ## Build code to export a programmable irq routing table
165 default HAVE_PIRQ_TABLE=1
166 default IRQ_SLOT_COUNT=18
169 ## Build code to export an x86 MP table
170 ## Useful for specifying IRQ routing values
172 default HAVE_MP_TABLE=1
175 ## Build code to provide ACPI support
177 default HAVE_ACPI_TABLES=1
178 default HAVE_MAINBOARD_RESOURCES=1
181 ## Build code to export a CMOS option table
183 default HAVE_OPTION_TABLE=1
186 ## Move the default coreboot cmos range off of AMD RTC registers
188 default LB_CKS_RANGE_START=49
189 default LB_CKS_RANGE_END=122
190 default LB_CKS_LOC=123
193 default CONFIG_CONSOLE_VGA=1
194 # There are some network option roms that don't work with
195 # coreboot's x86emu. Thus, we only execute the VGA option rom
197 default CONFIG_VGA_ROM_RUN=1
198 default CONFIG_PCI_ROM_RUN=0
202 ## Build code for SMP support
203 ## Only worry about 2 micro processors
206 default CONFIG_MAX_CPUS=4
207 default CONFIG_MAX_PHYSICAL_CPUS=2
208 default CONFIG_LOGICAL_CPUS=1
209 default CONFIG_AP_IN_SIPI_WAIT=1
212 ## enable CACHE_AS_RAM specifics
214 default USE_DCACHE_RAM=1
215 default DCACHE_RAM_SIZE=0x8000
216 default DCACHE_RAM_BASE=( 0xfff00000 - DCACHE_RAM_SIZE - 1024*1024)
217 default CONFIG_USE_PRINTK_IN_CAR=1
220 ## Build code to setup a generic IOAPIC
222 default CONFIG_IOAPIC=1
225 ## Clean up the motherboard id strings
227 default MAINBOARD_PART_NUMBER="986LCD-M"
228 default MAINBOARD_VENDOR= "KONTRON"
231 ### coreboot layout values
234 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
235 default ROM_IMAGE_SIZE = 65536
238 ## Use a small 8K stack
240 default STACK_SIZE=0x2000
243 ## Use a small 32K heap
245 default HEAP_SIZE=0x8000
249 ### Compute the location and size of where this firmware image
250 ### (coreboot plus bootloader) will live in the boot rom chip.
252 default FALLBACK_SIZE=131072
255 ## coreboot C code runs at this location in RAM
257 default _RAMBASE=0x00100000
260 ## Load the payload from the ROM
262 default CONFIG_ROM_PAYLOAD=1
265 ### Defaults of options that you may want to override in the target config file
269 ## The default compiler
271 default CC="$(CROSS_COMPILE)gcc -m32"
275 ## Disable the gdb stub by default
277 default CONFIG_GDB_STUB=0
280 ## The Serial Console
283 # To Enable the Serial Console
284 default CONFIG_CONSOLE_SERIAL8250=1
286 ## Select the serial console baud rate
287 default TTYS0_BAUD=115200
288 #default TTYS0_BAUD=57600
289 #default TTYS0_BAUD=38400
290 #default TTYS0_BAUD=19200
291 #default TTYS0_BAUD=9600
292 #default TTYS0_BAUD=4800
293 #default TTYS0_BAUD=2400
294 #default TTYS0_BAUD=1200
296 # Select the serial console base port
297 default TTYS0_BASE=0x3f8
299 # Select the serial protocol
300 # This defaults to 8 data bits, 1 stop bit, and no parity
301 default TTYS0_LCS=0x3
304 ### Select the coreboot loglevel
306 ## EMERG 1 system is unusable
307 ## ALERT 2 action must be taken immediately
308 ## CRIT 3 critical conditions
309 ## ERR 4 error conditions
310 ## WARNING 5 warning conditions
311 ## NOTICE 6 normal but significant condition
312 ## INFO 7 informational
313 ## DEBUG 8 debug-level messages
314 ## SPEW 9 Way too many details
316 ## Request this level of debugging output
317 default DEFAULT_CONSOLE_LOGLEVEL=5
318 ## At a maximum only compile in this level of debugging
319 default MAXIMUM_CONSOLE_LOGLEVEL=9
322 ## Select power on after power fail setting
323 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
328 default CONFIG_CBFS=1