2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007-2008 coresystems GmbH
6 ## This program is free software; you can redistribute it and/or
7 ## modify it under the terms of the GNU General Public License as
8 ## published by the Free Software Foundation; version 2 of
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 uses CONFIG_HAVE_MP_TABLE
24 uses CONFIG_HAVE_PIRQ_TABLE
25 uses CONFIG_IRQ_SLOT_COUNT
26 uses CONFIG_HAVE_OPTION_TABLE
27 uses CONFIG_USE_OPTION_TABLE
28 uses CONFIG_LB_CKS_RANGE_START
29 uses CONFIG_LB_CKS_RANGE_END
30 uses CONFIG_LB_CKS_LOC
31 uses CONFIG_HAVE_ACPI_TABLES
32 uses CONFIG_HAVE_ACPI_RESUME
33 uses CONFIG_HAVE_MAINBOARD_RESOURCES
36 uses CONFIG_LOGICAL_CPUS
37 uses CONFIG_AP_IN_SIPI_WAIT
39 uses CONFIG_MAX_PHYSICAL_CPUS
42 uses CONFIG_USE_FALLBACK_IMAGE
43 uses CONFIG_HAVE_FALLBACK_BOOT
44 uses CONFIG_FALLBACK_SIZE
46 uses CONFIG_ROM_SECTION_SIZE
47 uses CONFIG_ROM_IMAGE_SIZE
48 uses CONFIG_ROM_SECTION_SIZE
49 uses CONFIG_ROM_SECTION_OFFSET
51 uses CONFIG_ROM_PAYLOAD
52 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
53 uses CONFIG_PRECOMPRESSED_PAYLOAD
57 uses CONFIG_STACK_SIZE
59 uses CONFIG_USE_DCACHE_RAM
60 uses CONFIG_DCACHE_RAM_BASE
61 uses CONFIG_DCACHE_RAM_SIZE
63 uses CONFIG_USE_PRINTK_IN_CAR
64 uses CONFIG_XIP_ROM_BASE
65 uses CONFIG_XIP_ROM_SIZE
66 uses CONFIG_HAVE_HARD_RESET
67 uses CONFIG_HAVE_SMI_HANDLER
68 uses CONFIG_PCIE_CONFIGSPACE_HOLE
69 uses CONFIG_MMCONF_SUPPORT
70 uses CONFIG_MMCONF_BASE_ADDRESS
75 uses CONFIG_MAINBOARD_PART_NUMBER
76 uses CONFIG_MAINBOARD_VENDOR
77 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
78 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
80 uses CONFIG_UDELAY_LAPIC
82 uses CONFIG_CONSOLE_SERIAL8250
83 uses CONFIG_TTYS0_BAUD
84 uses CONFIG_TTYS0_BASE
86 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
87 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
88 uses CONFIG_CONSOLE_VGA
89 uses CONFIG_VGA_ROM_RUN
90 uses CONFIG_PCI_ROM_RUN
95 uses CONFIG_CROSS_COMPILE
99 uses CONFIG_MAX_REBOOT_CNT
100 uses CONFIG_USE_WATCHDOG_ON_BOOT
101 uses COREBOOT_EXTRA_VERSION
102 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
110 default CONFIG_MAX_REBOOT_CNT=3
113 ## Use the watchdog to break out of a lockup condition
115 default CONFIG_USE_WATCHDOG_ON_BOOT=0
118 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
120 default CONFIG_ROM_SIZE=1024*1024
124 ## Build code for the fallback boot
126 default CONFIG_HAVE_FALLBACK_BOOT=1
129 ## Delay timer options
131 default CONFIG_UDELAY_LAPIC=1
134 ## Build code to reset the motherboard from coreboot
136 default CONFIG_HAVE_HARD_RESET=1
141 default CONFIG_HAVE_SMI_HANDLER=1
144 ## Leave a hole for mmapped PCIe config space
147 default CONFIG_PCIE_CONFIGSPACE_HOLE=1
148 default CONFIG_MMCONF_SUPPORT=1
149 default CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
154 default CONFIG_GFXUMA=1
157 ## Build code to export a programmable irq routing table
159 default CONFIG_HAVE_PIRQ_TABLE=1
160 default CONFIG_IRQ_SLOT_COUNT=18
163 ## Build code to export an x86 MP table
164 ## Useful for specifying IRQ routing values
166 default CONFIG_HAVE_MP_TABLE=1
169 ## Build code to provide ACPI support
171 default CONFIG_HAVE_ACPI_TABLES=1
172 default CONFIG_HAVE_MAINBOARD_RESOURCES=1
173 default CONFIG_HAVE_ACPI_RESUME=1
176 ## Build code to export a CMOS option table
178 default CONFIG_HAVE_OPTION_TABLE=1
181 ## Move the default coreboot cmos range off of AMD RTC registers
183 default CONFIG_LB_CKS_RANGE_START=49
184 default CONFIG_LB_CKS_RANGE_END=122
185 default CONFIG_LB_CKS_LOC=123
188 default CONFIG_CONSOLE_VGA=1
189 # There are some network option roms that don't work with
190 # coreboot's x86emu. Thus, we only execute the VGA option rom
192 default CONFIG_VGA_ROM_RUN=1
193 default CONFIG_PCI_ROM_RUN=0
194 default CONFIG_DEBUG=0
197 ## Build code for SMP support
198 ## Only worry about 2 micro processors
201 default CONFIG_MAX_CPUS=4
202 default CONFIG_MAX_PHYSICAL_CPUS=2
203 default CONFIG_LOGICAL_CPUS=1
204 default CONFIG_AP_IN_SIPI_WAIT=1
207 ## enable CACHE_AS_RAM specifics
209 default CONFIG_USE_DCACHE_RAM=1
210 default CONFIG_DCACHE_RAM_SIZE=0x8000
211 default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024)
212 default CONFIG_USE_PRINTK_IN_CAR=1
215 ## Execute In Place settings
218 default CONFIG_XIP_ROM_SIZE = 128 * 1024
219 default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE - CONFIG_XIP_ROM_SIZE + CONFIG_ROM_IMAGE_SIZE )
222 ## Build code to setup a generic IOAPIC
224 default CONFIG_IOAPIC=1
227 ## Clean up the motherboard id strings
229 default CONFIG_MAINBOARD_PART_NUMBER="986LCD-M"
230 default CONFIG_MAINBOARD_VENDOR= "KONTRON"
233 ### coreboot layout values
236 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
237 default CONFIG_ROM_IMAGE_SIZE = 0x10000
240 ## Use a small 32K stack
242 default CONFIG_STACK_SIZE=0x8000
245 ## Use a small 32K heap
247 default CONFIG_HEAP_SIZE=0x8000
251 ### Compute the location and size of where this firmware image
252 ### (coreboot plus bootloader) will live in the boot rom chip.
254 default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
257 ## coreboot C code runs at this location in RAM
259 default CONFIG_RAMBASE=0x00100000
262 ## Load the payload from the ROM
264 default CONFIG_ROM_PAYLOAD=1
267 ### Defaults of options that you may want to override in the target config file
271 ## The default compiler
273 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
277 ## Disable the gdb stub by default
279 default CONFIG_GDB_STUB=0
282 ## The Serial Console
285 # To Enable the Serial Console
286 default CONFIG_CONSOLE_SERIAL8250=1
288 ## Select the serial console baud rate
289 default CONFIG_TTYS0_BAUD=115200
290 #default CONFIG_TTYS0_BAUD=57600
291 #default CONFIG_TTYS0_BAUD=38400
292 #default CONFIG_TTYS0_BAUD=19200
293 #default CONFIG_TTYS0_BAUD=9600
294 #default CONFIG_TTYS0_BAUD=4800
295 #default CONFIG_TTYS0_BAUD=2400
296 #default CONFIG_TTYS0_BAUD=1200
298 # Select the serial console base port
299 default CONFIG_TTYS0_BASE=0x3f8
301 # Select the serial protocol
302 # This defaults to 8 data bits, 1 stop bit, and no parity
303 default CONFIG_TTYS0_LCS=0x3
306 ### Select the coreboot loglevel
308 ## EMERG 1 system is unusable
309 ## ALERT 2 action must be taken immediately
310 ## CRIT 3 critical conditions
311 ## ERR 4 error conditions
312 ## WARNING 5 warning conditions
313 ## NOTICE 6 normal but significant condition
314 ## INFO 7 informational
315 ## CONFIG_DEBUG 8 debug-level messages
316 ## SPEW 9 Way too many details
318 ## Request this level of debugging output
319 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=5
320 ## At a maximum only compile in this level of debugging
321 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
324 ## Select power on after power fail setting
325 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"