src/mainboard/iwill/dk8x/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #define RAMINIT_SYSINFO 1
   5 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   6
   7 #define SET_NB_CFG_54 1
   8
   9 //used by raminit
  10 #define QRANK_DIMM_SUPPORT 1
  11
  12 //used by incoherent_ht
  13 //#define K8_ALLOCATE_IO_RANGE 1
  14
  15 //used by init_cpus and fidvid
  16 #define K8_SET_FIDVID 0
  17 //if we want to wait for core1 done before DQS training, set it to 0
  18 #define K8_SET_FIDVID_CORE0_ONLY 1
  19
  20 #if CONFIG_K8_REV_F_SUPPORT == 1
  21 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  22 #endif
  23
  24 #include <stdint.h>
  25 #include <string.h>
  26 #include <device/pci_def.h>
  27 #include <device/pci_ids.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <arch/romcc_io.h>
  31 #include <cpu/x86/lapic.h>
  32 #include "option_table.h"
  33 #include "pc80/mc146818rtc_early.c"
  34
  35 #if CONFIG_USE_FAILOVER_IMAGE==0
  36 #include "pc80/serial.c"
  37 #include "arch/i386/lib/console.c"
  38 #include <cpu/amd/model_fxx_rev.h>
  39 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  40 #include "northbridge/amd/amdk8/raminit.h"
  41 #include "cpu/amd/model_fxx/apic_timer.c"
  42 #endif
  43
  44
  45
  46 #include "cpu/x86/lapic/boot_cpu.c"
  47 #include "northbridge/amd/amdk8/reset_test.c"
  48
  49 #if CONFIG_USE_FAILOVER_IMAGE==0
  50 #include "cpu/x86/bist.h"
  51
  52 #include "lib/delay.c"
  53
  54 #include "northbridge/amd/amdk8/debug.c"
  55 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  56 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  57
  58 #include "northbridge/amd/amdk8/setup_resource_map.c"
  59
  60 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  61
  62 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  63
  64 /*
  65  * GPIO28 of 8111 will control H0_MEMRESET_L
  66  * GPIO29 of 8111 will control H1_MEMRESET_L
  67  */
  68 static void memreset_setup(void)
  69 {
  70         if (is_cpu_pre_c0()) {
  71                 /* Set the memreset low */
  72                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  73                 /* Ensure the BIOS has control of the memory lines */
  74                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  75         } else {
  76                 /* Ensure the CPU has controll of the memory lines */
  77                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  78         }
  79 }
  80
  81 static void memreset(int controllers, const struct mem_controller *ctrl)
  82 {
  83         if (is_cpu_pre_c0()) {
  84                 udelay(800);
  85                 /* Set memreset_high */
  86                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  87                 udelay(90);
  88         }
  89 }
  90
  91 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  92 {
  93 }
  94
  95 static inline int spd_read_byte(unsigned device, unsigned address)
  96 {
  97         return smbus_read_byte(device, address);
  98 }
  99
 100 #include "northbridge/amd/amdk8/amdk8.h"
 101 #include "northbridge/amd/amdk8/coherent_ht.c"
 102
 103 #include "northbridge/amd/amdk8/incoherent_ht.c"
 104
 105 #include "northbridge/amd/amdk8/raminit.c"
 106
 107 #include "lib/generic_sdram.c"
 108 #include "lib/ramtest.c"
 109
 110  /* tyan does not want the default */
 111 #include "northbridge/amd/amdk8/resourcemap.c"
 112
 113 #include "cpu/amd/dualcore/dualcore.c"
 114
 115 #define DIMM0 0x50
 116 #define DIMM1 0x51
 117 #define DIMM2 0x52
 118 #define DIMM3 0x53
 119 #define DIMM4 0x54
 120 #define DIMM5 0x55
 121 #define DIMM6 0x56
 122 #define DIMM7 0x57
 123
 124
 125 #include "cpu/amd/car/copy_and_run.c"
 126 #include "cpu/amd/car/post_cache_as_ram.c"
 127
 128 #include "cpu/amd/model_fxx/init_cpus.c"
 129
 130 #include "cpu/amd/model_fxx/fidvid.c"
 131 #endif
 132
 133 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 134 #include "northbridge/amd/amdk8/early_ht.c"
 135
 136 #if CONFIG_USE_FAILOVER_IMAGE==0
 137
 138 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 139 {
 140         static const uint16_t spd_addr[] = {
 141                         //first node
 142                         DIMM0, DIMM2, 0, 0,
 143                         DIMM1, DIMM3, 0, 0,
 144 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 145                         //second node
 146                         DIMM4, DIMM6, 0, 0,
 147                         DIMM5, DIMM7, 0, 0,
 148 #endif
 149
 150         };
 151
 152         struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 153
 154         int needs_reset; int i;
 155         unsigned bsp_apicid = 0;
 156
 157         if (!((cpu_init_detectedx) || (!boot_cpu()))) {
 158                 /* Nothing special needs to be done to find bus 0 */
 159                 /* Allow the HT devices to be found */
 160
 161                 enumerate_ht_chain();
 162
 163                 /* Setup the rom access for 4M */
 164                 amd8111_enable_rom();
 165         }
 166
 167         if (bist == 0) {
 168                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 169         }
 170
 171         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 172         uart_init();
 173         console_init();
 174
 175         /* Halt if there was a built in self test failure */
 176         report_bist_failure(bist);
 177
 178         print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
 179
 180         setup_default_resource_map();
 181
 182         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 183
 184 #if CONFIG_MEM_TRAIN_SEQ == 1
 185         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 186 #endif
 187         setup_coherent_ht_domain(); // routing table and start other core0
 188
 189         wait_all_core0_started();
 190 #if CONFIG_LOGICAL_CPUS==1
 191         // It is said that we should start core1 after all core0 launched
 192         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 193          * So here need to make sure last core0 is started, esp for two way system,
 194          * (there may be apic id conflicts in that case)
 195          */
 196         start_other_cores();
 197         wait_all_other_cores_started(bsp_apicid);
 198 #endif
 199
 200         /* it will set up chains and store link pair for optimization later */
 201         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 202
 203
 204 #if K8_SET_FIDVID == 1
 205
 206         {
 207                 msr_t msr;
 208                 msr=rdmsr(0xc0010042);
 209                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 210
 211         }
 212
 213         enable_fid_change();
 214
 215         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 216
 217         init_fidvid_bsp(bsp_apicid);
 218
 219         // show final fid and vid
 220         {
 221                 msr_t msr;
 222                 msr=rdmsr(0xc0010042);
 223                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 224
 225         }
 226 #endif
 227
 228         needs_reset = optimize_link_coherent_ht();
 229         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 230
 231         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 232         if (needs_reset) {
 233                 print_info("ht reset -\r\n");
 234                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 235         }
 236
 237         allow_all_aps_stop(bsp_apicid);
 238
 239         //It's the time to set ctrl in sysinfo now;
 240         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 241
 242         enable_smbus();
 243
 244 #if 0
 245         dump_smbus_registers();
 246 #endif
 247
 248         memreset_setup();
 249
 250         //do we need apci timer, tsc...., only debug need it for better output
 251         /* all ap stopped? */
 252         init_timer(); // Need to use TMICT to synconize FID/VID
 253         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 254
 255
 256 #if 0
 257         dump_pci_devices();
 258 #endif
 259
 260         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 261
 262 }
 263 #endif