src/mainboard/iwill/dk8x/romstage.c

   1 #if CONFIG_K8_REV_F_SUPPORT == 1
   2 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
   3 #endif
   4
   5 #include <stdint.h>
   6 #include <string.h>
   7 #include <device/pci_def.h>
   8 #include <device/pci_ids.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <pc80/mc146818rtc.h>
  13 #include <console/console.h>
  14 #include <cpu/amd/model_fxx_rev.h>
  15 #include "southbridge/amd/amd8111/early_smbus.c"
  16 #include "northbridge/amd/amdk8/raminit.h"
  17 #include "cpu/amd/model_fxx/apic_timer.c"
  18 #include "northbridge/amd/amdk8/reset_test.c"
  19 #include "cpu/x86/bist.h"
  20 #include "lib/delay.c"
  21 #include "northbridge/amd/amdk8/debug.c"
  22 #include "cpu/x86/mtrr/earlymtrr.c"
  23 #include "superio/winbond/w83627hf/early_serial.c"
  24 #include "northbridge/amd/amdk8/setup_resource_map.c"
  25 #include "southbridge/amd/amd8111/early_ctrl.c"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  28
  29 /*
  30  * GPIO28 of 8111 will control H0_MEMRESET_L
  31  * GPIO29 of 8111 will control H1_MEMRESET_L
  32  */
  33 static void memreset_setup(void)
  34 {
  35         if (is_cpu_pre_c0()) {
  36                 /* Set the memreset low. */
  37                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  38                 /* Ensure the BIOS has control of the memory lines. */
  39                 outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  40         } else {
  41                 /* Ensure the CPU has control of the memory lines. */
  42                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  43         }
  44 }
  45
  46 static void memreset(int controllers, const struct mem_controller *ctrl)
  47 {
  48         if (is_cpu_pre_c0()) {
  49                 udelay(800);
  50                 /* Set memreset high. */
  51                 outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  52                 udelay(90);
  53         }
  54 }
  55
  56 static void activate_spd_rom(const struct mem_controller *ctrl) { }
  57
  58 static inline int spd_read_byte(unsigned device, unsigned address)
  59 {
  60         return smbus_read_byte(device, address);
  61 }
  62
  63 #include "northbridge/amd/amdk8/amdk8.h"
  64 #include "northbridge/amd/amdk8/incoherent_ht.c"
  65 #include "northbridge/amd/amdk8/coherent_ht.c"
  66 #include "northbridge/amd/amdk8/raminit.c"
  67 #include "lib/generic_sdram.c"
  68 #include "northbridge/amd/amdk8/resourcemap.c"
  69 #include "cpu/amd/dualcore/dualcore.c"
  70 #include <spd.h>
  71 #include "cpu/amd/car/post_cache_as_ram.c"
  72 #include "cpu/amd/model_fxx/init_cpus.c"
  73 #include "cpu/amd/model_fxx/fidvid.c"
  74
  75 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  76 {
  77         static const uint16_t spd_addr[] = {
  78                 // first node
  79                 DIMM0, DIMM2, 0, 0,
  80                 DIMM1, DIMM3, 0, 0,
  81
  82                         // second node
  83                 DIMM4, DIMM6, 0, 0,
  84                 DIMM5, DIMM7, 0, 0,
  85         };
  86
  87         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
  88                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
  89         int needs_reset;
  90         unsigned bsp_apicid = 0;
  91
  92         if (bist == 0)
  93                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
  94
  95         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  96         console_init();
  97
  98         /* Halt if there was a built in self test failure */
  99         report_bist_failure(bist);
 100
 101         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 102
 103         setup_default_resource_map();
 104
 105         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 106
 107 #if CONFIG_MEM_TRAIN_SEQ == 1
 108         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 109 #endif
 110         setup_coherent_ht_domain(); // routing table and start other core0
 111
 112         wait_all_core0_started();
 113 #if CONFIG_LOGICAL_CPUS==1
 114         // It is said that we should start core1 after all core0 launched
 115         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 116          * So here need to make sure last core0 is started, esp for two way system,
 117          * (there may be apic id conflicts in that case)
 118          */
 119         start_other_cores();
 120         wait_all_other_cores_started(bsp_apicid);
 121 #endif
 122
 123         /* it will set up chains and store link pair for optimization later */
 124         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 125
 126 #if CONFIG_SET_FIDVID
 127         {
 128                 msr_t msr;
 129                 msr=rdmsr(0xc0010042);
 130                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 131         }
 132         enable_fid_change();
 133         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 134         init_fidvid_bsp(bsp_apicid);
 135         // show final fid and vid
 136         {
 137                 msr_t msr;
 138                 msr=rdmsr(0xc0010042);
 139                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 140         }
 141 #endif
 142
 143         needs_reset = optimize_link_coherent_ht();
 144         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 145
 146         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 147         if (needs_reset) {
 148                 print_info("ht reset -\n");
 149                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 150         }
 151
 152         allow_all_aps_stop(bsp_apicid);
 153
 154         //It's the time to set ctrl in sysinfo now;
 155         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 156
 157         enable_smbus();
 158
 159 #if 0
 160         dump_smbus_registers();
 161 #endif
 162
 163         memreset_setup();
 164
 165         //do we need apci timer, tsc...., only debug need it for better output
 166         /* all ap stopped? */
 167         init_timer(); // Need to use TMICT to synconize FID/VID
 168         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 169
 170 #if 0
 171         dump_pci_devices();
 172 #endif
 173
 174         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 175 }