src/mainboard/iwill/dk8x/auto.c

   1 #define ASSEMBLY 1
   2 #include <stdint.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <arch/cpu.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  15 #include "northbridge/amd/amdk8/raminit.h"
  16 #include "cpu/amd/model_fxx/apic_timer.c"
  17 #include "lib/delay.c"
  18 #include "cpu/x86/lapic/boot_cpu.c"
  19 #include "northbridge/amd/amdk8/reset_test.c"
  20 #include "northbridge/amd/amdk8/debug.c"
  21 #include <cpu/amd/model_fxx_rev.h>
  22
  23 #include "superio/nsc/pc87360/pc87360_early_serial.c"
  24 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  25 #include "cpu/x86/bist.h"
  26
  27 #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
  28
  29 static void hard_reset(void)
  30 {
  31         set_bios_reset();
  32
  33         /* enable cf9 */
  34         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  35         /* reset */
  36         outb(0x0e, 0x0cf9);
  37 }
  38
  39 static void soft_reset(void)
  40 {
  41         set_bios_reset();
  42         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  43 }
  44
  45 /*
  46  * GPIO28 of 8111 will control H0_MEMRESET_L
  47  * GPIO29 of 8111 will control H1_MEMRESET_L
  48  */
  49 static void memreset_setup(void)
  50 {
  51         if (is_cpu_pre_c0()) {
  52                 /* Set the memreset low */
  53                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  54                 /* Ensure the BIOS has control of the memory lines */
  55                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  56         }
  57         else {
  58                 /* Ensure the CPU has controll of the memory lines */
  59                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  60         }
  61 }
  62
  63 static void memreset(int controllers, const struct mem_controller *ctrl)
  64 {
  65         if (is_cpu_pre_c0()) {
  66                 udelay(800);
  67                 /* Set memreset_high */
  68                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  69                 udelay(90);
  70         }
  71 }
  72
  73 static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
  74 {
  75         /* Routing Table Node i
  76          *
  77          * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
  78          *  i:    0,    1,    2,    3,    4,    5,    6,    7
  79          *
  80          * [ 0: 3] Request Route
  81          *     [0] Route to this node
  82          *     [1] Route to Link 0
  83          *     [2] Route to Link 1
  84          *     [3] Route to Link 2
  85          * [11: 8] Response Route
  86          *     [0] Route to this node
  87          *     [1] Route to Link 0
  88          *     [2] Route to Link 1
  89          *     [3] Route to Link 2
  90          * [19:16] Broadcast route
  91          *     [0] Route to this node
  92          *     [1] Route to Link 0
  93          *     [2] Route to Link 1
  94          *     [3] Route to Link 2
  95          */
  96
  97         uint32_t ret=0x00010101; /* default row entry */
  98
  99         static const unsigned int rows_2p[2][2] = {
 100                 { 0x00050101, 0x00010404 },
 101                 { 0x00010404, 0x00050101 }
 102         };
 103
 104         if(maxnodes>2) {
 105                 print_debug("this mainboard is only designed for 2 cpus\r\n");
 106                 maxnodes=2;
 107         }
 108
 109
 110         if (!(node>=maxnodes || row>=maxnodes)) {
 111                 ret=rows_2p[node][row];
 112         }
 113
 114         return ret;
 115 }
 116
 117 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 118 {
 119         /* nothing to do */
 120 }
 121
 122 static inline int spd_read_byte(unsigned device, unsigned address)
 123 {
 124         return smbus_read_byte(device, address);
 125 }
 126
 127 #include "northbridge/amd/amdk8/raminit.c"
 128 #include "northbridge/amd/amdk8/coherent_ht.c"
 129 #include "northbridge/amd/amdk8/incoherent_ht.c"
 130 #include "sdram/generic_sdram.c"
 131 #include "northbridge/amd/amdk8/resourcemap.c"
 132 #include "cpu/amd/dualcore/dualcore.c"
 133
 134 #define FIRST_CPU  1
 135 #define SECOND_CPU 1
 136 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 137 static void main(unsigned long bist)
 138 {
 139         static const struct mem_controller cpu[] = {
 140 #if FIRST_CPU
 141                 {
 142                         .node_id = 0,
 143                         .f0 = PCI_DEV(0, 0x18, 0),
 144                         .f1 = PCI_DEV(0, 0x18, 1),
 145                         .f2 = PCI_DEV(0, 0x18, 2),
 146                         .f3 = PCI_DEV(0, 0x18, 3),
 147                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 148                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 149                 },
 150 #endif
 151 #if SECOND_CPU
 152                 {
 153                         .node_id = 1,
 154                         .f0 = PCI_DEV(0, 0x19, 0),
 155                         .f1 = PCI_DEV(0, 0x19, 1),
 156                         .f2 = PCI_DEV(0, 0x19, 2),
 157                         .f3 = PCI_DEV(0, 0x19, 3),
 158                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 159                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 160                 },
 161 #endif
 162         };
 163
 164         int needs_reset;
 165         unsigned nodeid;
 166
 167         if (bist == 0) {
 168                 k8_init_and_stop_secondaries();
 169         }
 170         /* Setup the console */
 171         pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
 172         uart_init();
 173         console_init();
 174
 175         /* Halt if there was a built in self test failure */
 176         report_bist_failure(bist);
 177
 178         setup_default_resource_map();
 179         needs_reset = setup_coherent_ht_domain();
 180         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 181         if (needs_reset) {
 182                 print_info("ht reset -\r\n");
 183                 soft_reset();
 184         }
 185
 186 #if 0
 187         print_pci_devices();
 188 #endif
 189         enable_smbus();
 190 #if 0
 191         dump_spd_registers(&cpu[0]);
 192 #endif
 193
 194         memreset_setup();
 195         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 196
 197 #if 1
 198         dump_pci_devices();
 199 #endif
 200 #if 0
 201         dump_pci_device(PCI_DEV(0, 0x18, 2));
 202 #endif
 203
 204         /* Check all of memory */
 205 #if 0
 206         msr_t msr;
 207         msr = rdmsr(TOP_MEM);
 208         print_debug("TOP_MEM: ");
 209         print_debug_hex32(msr.hi);
 210         print_debug_hex32(msr.lo);
 211         print_debug("\r\n");
 212 #endif
 213 #if 0
 214         ram_check(0x00000000, msr.lo);
 215 #endif
 216 #if 0
 217         static const struct {
 218                 unsigned long lo, hi;
 219         } check_addrs[] = {
 220                 /* Check 16MB of memory @ 0*/
 221                 { 0x00000000, 0x01000000 },
 222 #if TOTAL_CPUS > 1
 223                 /* Check 16MB of memory @ 2GB */
 224                 { 0x80000000, 0x81000000 },
 225 #endif
 226         };
 227         int i;
 228         for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
 229                 ram_check(check_addrs[i].lo, check_addrs[i].hi);
 230         }
 231 #endif
 232 }