2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
36 ## Set all of the defaults for an x86 architecture
42 ## Build the objects we have code for in this directory.
46 if HAVE_MP_TABLE object mptable.o end
47 if HAVE_PIRQ_TABLE object irq_tables.o end
54 depends "$(MAINBOARD)/failover.c ./romcc"
55 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
58 makerule ./failover.inc
59 depends "$(MAINBOARD)/failover.c ./romcc"
60 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
64 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
65 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
68 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
69 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
73 ## Build our 16 bit and 32 bit linuxBIOS entry code
75 mainboardinit cpu/x86/16bit/entry16.inc
76 mainboardinit cpu/x86/32bit/entry32.inc
77 ldscript /cpu/x86/16bit/entry16.lds
78 ldscript /cpu/x86/32bit/entry32.lds
81 ## Build our reset vector (This is where linuxBIOS is entered)
84 mainboardinit cpu/x86/16bit/reset16.inc
85 ldscript /cpu/x86/16bit/reset16.lds
87 mainboardinit cpu/x86/32bit/reset32.inc
88 ldscript /cpu/x86/32bit/reset32.lds
91 ### Should this be in the northbridge code?
92 mainboardinit arch/i386/lib/cpu_reset.inc
95 ## Include an id string (For safe flashing)
97 mainboardinit arch/i386/lib/id.inc
98 ldscript /arch/i386/lib/id.lds
101 ### This is the early phase of linuxBIOS startup
102 ### Things are delicate and we test to see if we should
103 ### failover to another image.
105 if USE_FALLBACK_IMAGE
106 ldscript /arch/i386/lib/failover.lds
107 mainboardinit ./failover.inc
111 ### O.k. We aren't just an intermediary anymore!
117 mainboardinit cpu/x86/fpu/enable_fpu.inc
118 mainboardinit cpu/x86/mmx/enable_mmx.inc
119 mainboardinit cpu/x86/sse/enable_sse.inc
120 mainboardinit ./auto.inc
121 mainboardinit cpu/x86/sse/disable_sse.inc
122 mainboardinit cpu/x86/mmx/disable_mmx.inc
125 ## Include the secondary Configuration files
130 chip northbridge/amd/amdk8/root_complex
131 device pci_domain 0 on
132 chip northbridge/amd/amdk8
133 device pci 18.0 on # northbridge
134 # devices on link 0, link 0 == LDT 0
135 chip southbridge/amd/amd8131
136 # the on/off keyword is mandatory
137 device pci 0.0 on end
138 device pci 0.1 on end
139 device pci 1.0 on end
140 device pci 1.1 on end
142 chip southbridge/amd/amd8111
143 # this "device pci 0.0" is the parent the next one
146 device pci 0.0 on end
147 device pci 0.1 on end
148 device pci 0.2 on end
149 device pci 1.0 off end
152 chip superio/winbond/w83627thf
153 device pnp 2e.0 on end
154 device pnp 2e.1 on end
155 device pnp 2e.2 on end
156 device pnp 2e.3 on end
157 device pnp 2e.4 on end
158 device pnp 2e.5 on end
159 device pnp 2e.6 on end
160 device pnp 2e.7 on end
161 device pnp 2e.8 on end
162 device pnp 2e.9 on end
163 device pnp 2e.a on end
166 device pci 1.1 on end
167 device pci 1.2 on end
168 device pci 1.3 on end
169 device pci 1.5 off end
170 device pci 1.6 off end
173 device pci 18.0 on end # LDT1
174 device pci 18.0 on end # LDT2
175 device pci 18.1 on end
176 device pci 18.2 on end
177 device pci 18.3 on end
179 chip northbridge/amd/amdk8
180 device pci 19.0 on end
181 device pci 19.0 on end
182 device pci 19.0 on end
183 device pci 19.1 on end
184 device pci 19.2 on end
185 device pci 19.3 on end
188 device apic_cluster 0 on
189 chip cpu/amd/socket_940
192 chip cpu/amd/socket_940