src/mainboard/iwill/dk8s2/romstage.c

   1 #define SET_NB_CFG_54 1
   2
   3 //used by init_cpus and fidvid
   4 #define SET_FIDVID 0
   5 //if we want to wait for core1 done before DQS training, set it to 0
   6 #define SET_FIDVID_CORE0_ONLY 1
   7
   8 #if CONFIG_K8_REV_F_SUPPORT == 1
   9 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  10 #endif
  11
  12 #include <stdint.h>
  13 #include <string.h>
  14 #include <device/pci_def.h>
  15 #include <device/pci_ids.h>
  16 #include <arch/io.h>
  17 #include <device/pnp_def.h>
  18 #include <arch/romcc_io.h>
  19 #include <cpu/x86/lapic.h>
  20 #include <pc80/mc146818rtc.h>
  21
  22 #include <console/console.h>
  23 #include <cpu/amd/model_fxx_rev.h>
  24 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  25 #include "northbridge/amd/amdk8/raminit.h"
  26 #include "cpu/amd/model_fxx/apic_timer.c"
  27
  28 #include "cpu/x86/lapic/boot_cpu.c"
  29 #include "northbridge/amd/amdk8/reset_test.c"
  30
  31 #include "cpu/x86/bist.h"
  32
  33 #include "lib/delay.c"
  34
  35 #include "northbridge/amd/amdk8/debug.c"
  36 #include "cpu/x86/mtrr/earlymtrr.c"
  37 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  38
  39 #include "northbridge/amd/amdk8/setup_resource_map.c"
  40
  41 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  42
  43 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  44
  45 /*
  46  * GPIO28 of 8111 will control H0_MEMRESET_L
  47  * GPIO29 of 8111 will control H1_MEMRESET_L
  48  */
  49 static void memreset_setup(void)
  50 {
  51         if (is_cpu_pre_c0()) {
  52                 /* Set the memreset low */
  53                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  54                 /* Ensure the BIOS has control of the memory lines */
  55                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  56         } else {
  57                 /* Ensure the CPU has controll of the memory lines */
  58                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  59         }
  60 }
  61
  62 static void memreset(int controllers, const struct mem_controller *ctrl)
  63 {
  64         if (is_cpu_pre_c0()) {
  65                 udelay(800);
  66                 /* Set memreset_high */
  67                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  68                 udelay(90);
  69         }
  70 }
  71
  72 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  73 {
  74 }
  75
  76 static inline int spd_read_byte(unsigned device, unsigned address)
  77 {
  78         return smbus_read_byte(device, address);
  79 }
  80
  81 #include "northbridge/amd/amdk8/amdk8.h"
  82 #include "northbridge/amd/amdk8/incoherent_ht.c"
  83 #include "northbridge/amd/amdk8/coherent_ht.c"
  84 #include "northbridge/amd/amdk8/raminit.c"
  85 #include "lib/generic_sdram.c"
  86
  87  /* tyan does not want the default */
  88 #include "northbridge/amd/amdk8/resourcemap.c"
  89
  90 #include "cpu/amd/dualcore/dualcore.c"
  91
  92 #define DIMM0 0x50
  93 #define DIMM1 0x51
  94 #define DIMM2 0x52
  95 #define DIMM3 0x53
  96 #define DIMM4 0x54
  97 #define DIMM5 0x55
  98 #define DIMM6 0x56
  99 #define DIMM7 0x57
 100
 101 #include "cpu/amd/car/post_cache_as_ram.c"
 102
 103 #include "cpu/amd/model_fxx/init_cpus.c"
 104
 105 #include "cpu/amd/model_fxx/fidvid.c"
 106
 107 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 108 #include "northbridge/amd/amdk8/early_ht.c"
 109
 110 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 111 {
 112         static const uint16_t spd_addr[] = {
 113                         // first node
 114                         DIMM0, DIMM2, 0, 0,
 115                         DIMM1, DIMM3, 0, 0,
 116
 117                         // second node
 118                         DIMM4, DIMM6, 0, 0,
 119                         DIMM5, DIMM7, 0, 0,
 120         };
 121
 122         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 123                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 124
 125         int needs_reset;
 126         unsigned bsp_apicid = 0;
 127
 128         if (!cpu_init_detectedx && boot_cpu()) {
 129                 /* Nothing special needs to be done to find bus 0 */
 130                 /* Allow the HT devices to be found */
 131
 132                 enumerate_ht_chain();
 133
 134                 /* Setup the rom access for 4M */
 135                 amd8111_enable_rom();
 136         }
 137
 138         if (bist == 0) {
 139                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 140         }
 141
 142         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 143         uart_init();
 144         console_init();
 145
 146         /* Halt if there was a built in self test failure */
 147         report_bist_failure(bist);
 148
 149         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 150
 151         setup_default_resource_map();
 152
 153         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 154
 155 #if CONFIG_MEM_TRAIN_SEQ == 1
 156         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 157 #endif
 158         setup_coherent_ht_domain(); // routing table and start other core0
 159
 160         wait_all_core0_started();
 161 #if CONFIG_LOGICAL_CPUS==1
 162         // It is said that we should start core1 after all core0 launched
 163         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 164          * So here need to make sure last core0 is started, esp for two way system,
 165          * (there may be apic id conflicts in that case)
 166          */
 167         start_other_cores();
 168         wait_all_other_cores_started(bsp_apicid);
 169 #endif
 170
 171         /* it will set up chains and store link pair for optimization later */
 172         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 173
 174 #if SET_FIDVID == 1
 175
 176         {
 177                 msr_t msr;
 178                 msr=rdmsr(0xc0010042);
 179                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 180
 181         }
 182
 183         enable_fid_change();
 184
 185         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 186
 187         init_fidvid_bsp(bsp_apicid);
 188
 189         // show final fid and vid
 190         {
 191                 msr_t msr;
 192                 msr=rdmsr(0xc0010042);
 193                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 194
 195         }
 196 #endif
 197
 198         needs_reset = optimize_link_coherent_ht();
 199         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 200
 201         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 202         if (needs_reset) {
 203                 print_info("ht reset -\n");
 204                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 205         }
 206
 207         allow_all_aps_stop(bsp_apicid);
 208
 209         //It's the time to set ctrl in sysinfo now;
 210         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 211
 212         enable_smbus();
 213
 214 #if 0
 215         dump_smbus_registers();
 216 #endif
 217
 218         memreset_setup();
 219
 220         //do we need apci timer, tsc...., only debug need it for better output
 221         /* all ap stopped? */
 222         init_timer(); // Need to use TMICT to synconize FID/VID
 223         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 224
 225 #if 0
 226         dump_pci_devices();
 227 #endif
 228
 229         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 230
 231 }
 232