src/mainboard/iwill/dk8s2/romstage.c

   1 #define SET_NB_CFG_54 1
   2
   3 //used by raminit
   4 #define QRANK_DIMM_SUPPORT 1
   5
   6 //used by incoherent_ht
   7 //#define K8_ALLOCATE_IO_RANGE 1
   8
   9 //used by init_cpus and fidvid
  10 #define SET_FIDVID 0
  11 //if we want to wait for core1 done before DQS training, set it to 0
  12 #define SET_FIDVID_CORE0_ONLY 1
  13
  14 #if CONFIG_K8_REV_F_SUPPORT == 1
  15 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  16 #endif
  17
  18 #include <stdint.h>
  19 #include <string.h>
  20 #include <device/pci_def.h>
  21 #include <device/pci_ids.h>
  22 #include <arch/io.h>
  23 #include <device/pnp_def.h>
  24 #include <arch/romcc_io.h>
  25 #include <cpu/x86/lapic.h>
  26 #include <pc80/mc146818rtc.h>
  27
  28 #include <console/console.h>
  29 #include <cpu/amd/model_fxx_rev.h>
  30 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  31 #include "northbridge/amd/amdk8/raminit.h"
  32 #include "cpu/amd/model_fxx/apic_timer.c"
  33
  34 #include "cpu/x86/lapic/boot_cpu.c"
  35 #include "northbridge/amd/amdk8/reset_test.c"
  36
  37 #include "cpu/x86/bist.h"
  38
  39 #include "lib/delay.c"
  40
  41 #include "northbridge/amd/amdk8/debug.c"
  42 #include "cpu/x86/mtrr/earlymtrr.c"
  43 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  44
  45 #include "northbridge/amd/amdk8/setup_resource_map.c"
  46
  47 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  48
  49 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  50
  51 /*
  52  * GPIO28 of 8111 will control H0_MEMRESET_L
  53  * GPIO29 of 8111 will control H1_MEMRESET_L
  54  */
  55 static void memreset_setup(void)
  56 {
  57         if (is_cpu_pre_c0()) {
  58                 /* Set the memreset low */
  59                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  60                 /* Ensure the BIOS has control of the memory lines */
  61                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  62         } else {
  63                 /* Ensure the CPU has controll of the memory lines */
  64                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  65         }
  66 }
  67
  68 static void memreset(int controllers, const struct mem_controller *ctrl)
  69 {
  70         if (is_cpu_pre_c0()) {
  71                 udelay(800);
  72                 /* Set memreset_high */
  73                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  74                 udelay(90);
  75         }
  76 }
  77
  78 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  79 {
  80 }
  81
  82 static inline int spd_read_byte(unsigned device, unsigned address)
  83 {
  84         return smbus_read_byte(device, address);
  85 }
  86
  87 #include "northbridge/amd/amdk8/amdk8.h"
  88 #include "northbridge/amd/amdk8/incoherent_ht.c"
  89 #include "northbridge/amd/amdk8/coherent_ht.c"
  90 #include "northbridge/amd/amdk8/raminit.c"
  91 #include "lib/generic_sdram.c"
  92
  93  /* tyan does not want the default */
  94 #include "northbridge/amd/amdk8/resourcemap.c"
  95
  96 #include "cpu/amd/dualcore/dualcore.c"
  97
  98 #define DIMM0 0x50
  99 #define DIMM1 0x51
 100 #define DIMM2 0x52
 101 #define DIMM3 0x53
 102 #define DIMM4 0x54
 103 #define DIMM5 0x55
 104 #define DIMM6 0x56
 105 #define DIMM7 0x57
 106
 107 #include "cpu/amd/car/post_cache_as_ram.c"
 108
 109 #include "cpu/amd/model_fxx/init_cpus.c"
 110
 111 #include "cpu/amd/model_fxx/fidvid.c"
 112
 113 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 114 #include "northbridge/amd/amdk8/early_ht.c"
 115
 116 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 117 {
 118         static const uint16_t spd_addr[] = {
 119                         // first node
 120                         DIMM0, DIMM2, 0, 0,
 121                         DIMM1, DIMM3, 0, 0,
 122
 123                         // second node
 124                         DIMM4, DIMM6, 0, 0,
 125                         DIMM5, DIMM7, 0, 0,
 126         };
 127
 128         struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
 129                 + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 130
 131         int needs_reset;
 132         unsigned bsp_apicid = 0;
 133
 134         if (!cpu_init_detectedx && boot_cpu()) {
 135                 /* Nothing special needs to be done to find bus 0 */
 136                 /* Allow the HT devices to be found */
 137
 138                 enumerate_ht_chain();
 139
 140                 /* Setup the rom access for 4M */
 141                 amd8111_enable_rom();
 142         }
 143
 144         if (bist == 0) {
 145                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 146         }
 147
 148         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 149         uart_init();
 150         console_init();
 151
 152         /* Halt if there was a built in self test failure */
 153         report_bist_failure(bist);
 154
 155         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 156
 157         setup_default_resource_map();
 158
 159         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 160
 161 #if CONFIG_MEM_TRAIN_SEQ == 1
 162         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 163 #endif
 164         setup_coherent_ht_domain(); // routing table and start other core0
 165
 166         wait_all_core0_started();
 167 #if CONFIG_LOGICAL_CPUS==1
 168         // It is said that we should start core1 after all core0 launched
 169         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 170          * So here need to make sure last core0 is started, esp for two way system,
 171          * (there may be apic id conflicts in that case)
 172          */
 173         start_other_cores();
 174         wait_all_other_cores_started(bsp_apicid);
 175 #endif
 176
 177         /* it will set up chains and store link pair for optimization later */
 178         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 179
 180 #if SET_FIDVID == 1
 181
 182         {
 183                 msr_t msr;
 184                 msr=rdmsr(0xc0010042);
 185                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 186
 187         }
 188
 189         enable_fid_change();
 190
 191         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 192
 193         init_fidvid_bsp(bsp_apicid);
 194
 195         // show final fid and vid
 196         {
 197                 msr_t msr;
 198                 msr=rdmsr(0xc0010042);
 199                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 200
 201         }
 202 #endif
 203
 204         needs_reset = optimize_link_coherent_ht();
 205         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 206
 207         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 208         if (needs_reset) {
 209                 print_info("ht reset -\n");
 210                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 211         }
 212
 213         allow_all_aps_stop(bsp_apicid);
 214
 215         //It's the time to set ctrl in sysinfo now;
 216         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 217
 218         enable_smbus();
 219
 220 #if 0
 221         dump_smbus_registers();
 222 #endif
 223
 224         memreset_setup();
 225
 226         //do we need apci timer, tsc...., only debug need it for better output
 227         /* all ap stopped? */
 228         init_timer(); // Need to use TMICT to synconize FID/VID
 229         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 230
 231 #if 0
 232         dump_pci_devices();
 233 #endif
 234
 235         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 236
 237 }
 238