src/mainboard/iwill/dk8s2/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (coreboot plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The coreboot bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of coreboot will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up coreboot,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 ##
  36 ## Set all of the defaults for an x86 architecture
  37 ##
  38
  39 arch i386 end
  40
  41 ##
  42 ## Build the objects we have code for in this directory.
  43 ##
  44
  45 driver mainboard.o
  46 if HAVE_MP_TABLE object mptable.o end
  47 if HAVE_PIRQ_TABLE object irq_tables.o end
  48 #object reset.o
  49
  50 ## ATI Rage XL framebuffering graphics driver
  51 dir /drivers/ati/ragexl
  52
  53 if CONFIG_USE_INIT
  54
  55 makerule ./auto.o
  56         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  57         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  58 end
  59
  60 else
  61
  62 makerule ./auto.inc
  63         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  64         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  65         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  66         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  67 end
  68
  69 end
  70
  71 ##
  72 ## Build our 16 bit and 32 bit coreboot entry code
  73 ##
  74 if USE_FALLBACK_IMAGE
  75         mainboardinit cpu/x86/16bit/entry16.inc
  76         ldscript /cpu/x86/16bit/entry16.lds
  77 end
  78
  79 mainboardinit cpu/x86/32bit/entry32.inc
  80
  81         if CONFIG_USE_INIT
  82                 ldscript /cpu/x86/32bit/entry32.lds
  83         end
  84
  85         if CONFIG_USE_INIT
  86                 ldscript      /cpu/amd/car/cache_as_ram.lds
  87         end
  88
  89 ##
  90 ## Build our reset vector (This is where coreboot is entered)
  91 ##
  92 if USE_FALLBACK_IMAGE
  93         mainboardinit cpu/x86/16bit/reset16.inc
  94         ldscript /cpu/x86/16bit/reset16.lds
  95 else
  96         mainboardinit cpu/x86/32bit/reset32.inc
  97         ldscript /cpu/x86/32bit/reset32.lds
  98 end
  99
 100 ##
 101 ## Include an id string (For safe flashing)
 102 ##
 103 mainboardinit arch/i386/lib/id.inc
 104 ldscript /arch/i386/lib/id.lds
 105
 106 ##
 107 ## Setup Cache-As-Ram
 108 ##
 109 mainboardinit cpu/amd/car/cache_as_ram.inc
 110
 111 ###
 112 ### This is the early phase of coreboot startup
 113 ### Things are delicate and we test to see if we should
 114 ### failover to another image.
 115 ###
 116 if USE_FALLBACK_IMAGE
 117        ldscript /arch/i386/lib/failover.lds
 118 end
 119
 120 ###
 121 ### O.k. We aren't just an intermediary anymore!
 122 ###
 123
 124 ##
 125 ## Setup RAM
 126 ##
 127 if CONFIG_USE_INIT
 128 initobject auto.o
 129 else
 130 mainboardinit ./auto.inc
 131 end
 132
 133 ##
 134 ## Include the secondary Configuration files
 135 ##
 136 config chip.h
 137
 138 # config for iwill/dk8s2
 139 chip northbridge/amd/amdk8/root_complex
 140         device pci_domain 0 on
 141                 chip northbridge/amd/amdk8
 142                         device pci 18.0 on # LDT 0
 143                                 chip southbridge/amd/amd8131
 144                                         device pci 0.0 on end
 145                                         device pci 0.1 on end
 146                                         device pci 1.0 on end
 147                                         device pci 1.1 on end
 148                                 end
 149                                 chip southbridge/amd/amd8111
 150                                         # this "device pci 0.0" is the parent the next one
 151                                         # PCI bridge
 152                                         device pci 0.0 on
 153                                                 device pci 0.0 on end
 154                                                 device pci 0.1 on end
 155                                                 device pci 0.2 on end
 156                                                 device pci 1.0 off end
 157                                         end
 158                                         device pci 1.0 on
 159                                                 chip superio/winbond/w83627hf
 160                                                         device pnp  2e.0 on      # Floppy
 161                                                                  io 0x60 = 0x3f0
 162                                                                 irq 0x70 = 6
 163                                                                 drq 0x74 = 2
 164                                                         end
 165                                                         device pnp  2e.1 off     # Parallel Port
 166                                                                  io 0x60 = 0x378
 167                                                                 irq 0x70 = 7
 168                                                         end
 169                                                         device pnp  2e.2 on      # Com1
 170                                                                  io 0x60 = 0x3f8
 171                                                                 irq 0x70 = 4
 172                                                         end
 173                                                         device pnp  2e.3 off     # Com2
 174                                                                 io 0x60 = 0x2f8
 175                                                                 irq 0x70 = 3
 176                                                         end
 177                                                         device pnp  2e.5 on      # Keyboard
 178                                                                  io 0x60 = 0x60
 179                                                                  io 0x62 = 0x64
 180                                                                irq 0x70 = 1
 181                                                                 irq 0x72 = 12
 182                                                         end
 183                                                         device pnp  2e.6 off end # CIR
 184                                                         device pnp  2e.7 off end # GAME_MIDI_GIPO1
 185                                                         device pnp  2e.8 off end # GPIO2
 186                                                         device pnp  2e.9 off end # GPIO3
 187                                                         device pnp  2e.a off end # ACPI
 188                                                         device pnp  2e.b on      # HW Monitor
 189                                                                  io 0x60 = 0x290
 190                                                         end
 191                                                         register "com1" = "{1}"
 192                                                 #       register "com1" = "{1, 0, 0x3f8, 4}"
 193                                                 #       register "lpt" = "{1}"
 194                                                 end
 195                                         end
 196                                         device pci 1.1 on end
 197                                         device pci 1.2 on end
 198                                         device pci 1.3 on end
 199                                         device pci 1.5 off end
 200                                         device pci 1.6 off end
 201                                 end
 202                         end # LDT0
 203                         device pci 18.0 on end # LDT1
 204                         device pci 18.0 on end # LDT2
 205                         device pci 18.1 on end
 206                         device pci 18.2 on end
 207                         device pci 18.3 on end
 208                 end
 209                 chip northbridge/amd/amdk8
 210                         device pci 19.0 on end
 211                         device pci 19.0 on end
 212                         device pci 19.0 on end
 213                         device pci 19.1 on end
 214                         device pci 19.2 on end
 215                         device pci 19.3 on end
 216                 end
 217         end
 218         device apic_cluster 0 on
 219                 chip cpu/amd/socket_940
 220                         device apic 0 on end
 221                 end
 222                 chip cpu/amd/socket_940
 223                         device apic 1 on end
 224                 end
 225         end
 226 end
 227