src/mainboard/iwill/dk8s2/Config.lb

   1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
   2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
   3 include /config/nofailovercalculation.lb
   4
   5 ##
   6 ## Set all of the defaults for an x86 architecture
   7 ##
   8
   9 arch i386 end
  10
  11 ##
  12 ## Build the objects we have code for in this directory.
  13 ##
  14
  15 driver mainboard.o
  16 if CONFIG_GENERATE_MP_TABLE object mptable.o end
  17 if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
  18 #object reset.o
  19
  20 ## ATI Rage XL framebuffering graphics driver
  21 dir /drivers/ati/ragexl
  22
  23 if CONFIG_USE_INIT
  24
  25 makerule ./auto.o
  26         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  27         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  28 end
  29
  30 else
  31
  32 makerule ./auto.inc
  33         depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
  34         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
  35         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  36         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  37 end
  38
  39 end
  40
  41 ##
  42 ## Build our 16 bit and 32 bit coreboot entry code
  43 ##
  44 if CONFIG_USE_FALLBACK_IMAGE
  45         mainboardinit cpu/x86/16bit/entry16.inc
  46         ldscript /cpu/x86/16bit/entry16.lds
  47 end
  48
  49 mainboardinit cpu/x86/32bit/entry32.inc
  50
  51         if CONFIG_USE_INIT
  52                 ldscript /cpu/x86/32bit/entry32.lds
  53         end
  54
  55         if CONFIG_USE_INIT
  56                 ldscript      /cpu/amd/car/cache_as_ram.lds
  57         end
  58
  59 ##
  60 ## Build our reset vector (This is where coreboot is entered)
  61 ##
  62 if CONFIG_USE_FALLBACK_IMAGE
  63         mainboardinit cpu/x86/16bit/reset16.inc
  64         ldscript /cpu/x86/16bit/reset16.lds
  65 else
  66         mainboardinit cpu/x86/32bit/reset32.inc
  67         ldscript /cpu/x86/32bit/reset32.lds
  68 end
  69
  70 ##
  71 ## Include an id string (For safe flashing)
  72 ##
  73 mainboardinit arch/i386/lib/id.inc
  74 ldscript /arch/i386/lib/id.lds
  75
  76 ##
  77 ## Setup Cache-As-Ram
  78 ##
  79 mainboardinit cpu/amd/car/cache_as_ram.inc
  80
  81 ###
  82 ### This is the early phase of coreboot startup
  83 ### Things are delicate and we test to see if we should
  84 ### failover to another image.
  85 ###
  86 if CONFIG_USE_FALLBACK_IMAGE
  87        ldscript /arch/i386/lib/failover.lds
  88 end
  89
  90 ###
  91 ### O.k. We aren't just an intermediary anymore!
  92 ###
  93
  94 ##
  95 ## Setup RAM
  96 ##
  97 if CONFIG_USE_INIT
  98 initobject auto.o
  99 else
 100 mainboardinit ./auto.inc
 101 end
 102
 103 ##
 104 ## Include the secondary Configuration files
 105 ##
 106 config chip.h
 107
 108 # config for iwill/dk8s2
 109 chip northbridge/amd/amdk8/root_complex
 110         device pci_domain 0 on
 111                 chip northbridge/amd/amdk8
 112                         device pci 18.0 on # LDT 0
 113                                 chip southbridge/amd/amd8131
 114                                         device pci 0.0 on end
 115                                         device pci 0.1 on end
 116                                         device pci 1.0 on end
 117                                         device pci 1.1 on end
 118                                 end
 119                                 chip southbridge/amd/amd8111
 120                                         # this "device pci 0.0" is the parent the next one
 121                                         # PCI bridge
 122                                         device pci 0.0 on
 123                                                 device pci 0.0 on end
 124                                                 device pci 0.1 on end
 125                                                 device pci 0.2 on end
 126                                                 device pci 1.0 off end
 127                                         end
 128                                         device pci 1.0 on
 129                                                 chip superio/winbond/w83627hf
 130                                                         device pnp  2e.0 on      # Floppy
 131                                                                  io 0x60 = 0x3f0
 132                                                                 irq 0x70 = 6
 133                                                                 drq 0x74 = 2
 134                                                         end
 135                                                         device pnp  2e.1 off     # Parallel Port
 136                                                                  io 0x60 = 0x378
 137                                                                 irq 0x70 = 7
 138                                                         end
 139                                                         device pnp  2e.2 on      # Com1
 140                                                                  io 0x60 = 0x3f8
 141                                                                 irq 0x70 = 4
 142                                                         end
 143                                                         device pnp  2e.3 off     # Com2
 144                                                                 io 0x60 = 0x2f8
 145                                                                 irq 0x70 = 3
 146                                                         end
 147                                                         device pnp  2e.5 on      # Keyboard
 148                                                                  io 0x60 = 0x60
 149                                                                  io 0x62 = 0x64
 150                                                                irq 0x70 = 1
 151                                                                 irq 0x72 = 12
 152                                                         end
 153                                                         device pnp  2e.6 off end # CIR
 154                                                         device pnp  2e.7 off end # GAME_MIDI_GIPO1
 155                                                         device pnp  2e.8 off end # GPIO2
 156                                                         device pnp  2e.9 off end # GPIO3
 157                                                         device pnp  2e.a off end # ACPI
 158                                                         device pnp  2e.b on      # HW Monitor
 159                                                                  io 0x60 = 0x290
 160                                                         end
 161                                                         register "com1" = "{1}"
 162                                                 #       register "com1" = "{1, 0, 0x3f8, 4}"
 163                                                 #       register "lpt" = "{1}"
 164                                                 end
 165                                         end
 166                                         device pci 1.1 on end
 167                                         device pci 1.2 on end
 168                                         device pci 1.3 on end
 169                                         device pci 1.5 off end
 170                                         device pci 1.6 off end
 171                                 end
 172                         end # LDT0
 173                         device pci 18.0 on end # LDT1
 174                         device pci 18.0 on end # LDT2
 175                         device pci 18.1 on end
 176                         device pci 18.2 on end
 177                         device pci 18.3 on end
 178                 end
 179                 chip northbridge/amd/amdk8
 180                         device pci 19.0 on end
 181                         device pci 19.0 on end
 182                         device pci 19.0 on end
 183                         device pci 19.1 on end
 184                         device pci 19.2 on end
 185                         device pci 19.3 on end
 186                 end
 187         end
 188         device apic_cluster 0 on
 189                 chip cpu/amd/socket_940
 190                         device apic 0 on end
 191                 end
 192                 chip cpu/amd/socket_940
 193                         device apic 1 on end
 194                 end
 195         end
 196 end
 197