4 #define RAMINIT_SYSINFO 1
5 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
7 #define SET_NB_CFG_54 1
10 #define QRANK_DIMM_SUPPORT 1
12 //used by incoherent_ht
13 //#define K8_ALLOCATE_IO_RANGE 1
15 //used by init_cpus and fidvid
16 #define K8_SET_FIDVID 0
17 //if we want to wait for core1 done before DQS training, set it to 0
18 #define K8_SET_FIDVID_CORE0_ONLY 1
20 #if CONFIG_K8_REV_F_SUPPORT == 1
21 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
26 #include <device/pci_def.h>
27 #include <device/pci_ids.h>
29 #include <device/pnp_def.h>
30 #include <arch/romcc_io.h>
31 #include <cpu/x86/lapic.h>
32 #include "option_table.h"
33 #include "pc80/mc146818rtc_early.c"
35 #if CONFIG_USE_FAILOVER_IMAGE==0
36 #include "pc80/serial.c"
37 #include "arch/i386/lib/console.c"
38 #include <cpu/amd/model_fxx_rev.h>
39 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
40 #include "northbridge/amd/amdk8/raminit.h"
41 #include "cpu/amd/model_fxx/apic_timer.c"
46 #include "cpu/x86/lapic/boot_cpu.c"
47 #include "northbridge/amd/amdk8/reset_test.c"
49 #if CONFIG_USE_FAILOVER_IMAGE==0
50 #include "cpu/x86/bist.h"
52 #include "lib/delay.c"
54 #include "northbridge/amd/amdk8/debug.c"
55 #include "cpu/amd/mtrr/amd_earlymtrr.c"
56 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
58 #include "northbridge/amd/amdk8/setup_resource_map.c"
60 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
62 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
65 * GPIO28 of 8111 will control H0_MEMRESET_L
66 * GPIO29 of 8111 will control H1_MEMRESET_L
68 static void memreset_setup(void)
70 if (is_cpu_pre_c0()) {
71 /* Set the memreset low */
72 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
73 /* Ensure the BIOS has control of the memory lines */
74 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
76 /* Ensure the CPU has controll of the memory lines */
77 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
81 static void memreset(int controllers, const struct mem_controller *ctrl)
83 if (is_cpu_pre_c0()) {
85 /* Set memreset_high */
86 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
91 static inline void activate_spd_rom(const struct mem_controller *ctrl)
95 static inline int spd_read_byte(unsigned device, unsigned address)
97 return smbus_read_byte(device, address);
100 #include "northbridge/amd/amdk8/amdk8.h"
101 #include "northbridge/amd/amdk8/coherent_ht.c"
103 #include "northbridge/amd/amdk8/incoherent_ht.c"
105 #include "northbridge/amd/amdk8/raminit.c"
107 #include "lib/generic_sdram.c"
108 #include "lib/ramtest.c"
110 /* tyan does not want the default */
111 #include "resourcemap.c"
113 #include "cpu/amd/dualcore/dualcore.c"
125 #include "cpu/amd/car/copy_and_run.c"
126 #include "cpu/amd/car/post_cache_as_ram.c"
128 #include "cpu/amd/model_fxx/init_cpus.c"
130 #include "cpu/amd/model_fxx/fidvid.c"
133 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
134 #include "northbridge/amd/amdk8/early_ht.c"
136 #if CONFIG_USE_FAILOVER_IMAGE==0
138 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
140 static const uint16_t spd_addr[] = {
144 #if CONFIG_MAX_PHYSICAL_CPUS > 1
152 struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
154 int needs_reset; int i;
155 unsigned bsp_apicid = 0;
157 if (!((cpu_init_detectedx) || (!boot_cpu()))) {
158 /* Nothing special needs to be done to find bus 0 */
159 /* Allow the HT devices to be found */
161 enumerate_ht_chain();
163 /* Setup the rom access for 4M */
164 amd8111_enable_rom();
168 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
171 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
175 /* Halt if there was a built in self test failure */
176 report_bist_failure(bist);
178 print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
180 setup_mb_resource_map();
182 print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
184 #if CONFIG_MEM_TRAIN_SEQ == 1
185 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
187 setup_coherent_ht_domain(); // routing table and start other core0
189 wait_all_core0_started();
190 #if CONFIG_LOGICAL_CPUS==1
191 // It is said that we should start core1 after all core0 launched
192 /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
193 * So here need to make sure last core0 is started, esp for two way system,
194 * (there may be apic id conflicts in that case)
197 wait_all_other_cores_started(bsp_apicid);
200 /* it will set up chains and store link pair for optimization later */
201 ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
204 #if K8_SET_FIDVID == 1
208 msr=rdmsr(0xc0010042);
209 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
215 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
217 init_fidvid_bsp(bsp_apicid);
219 // show final fid and vid
222 msr=rdmsr(0xc0010042);
223 print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
228 needs_reset = optimize_link_coherent_ht();
229 needs_reset |= optimize_link_incoherent_ht(sysinfo);
231 // fidvid change will issue one LDTSTOP and the HT change will be effective too
233 print_info("ht reset -\r\n");
234 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
237 allow_all_aps_stop(bsp_apicid);
239 //It's the time to set ctrl in sysinfo now;
240 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
245 dump_smbus_registers();
250 //do we need apci timer, tsc...., only debug need it for better output
251 /* all ap stopped? */
252 init_timer(); // Need to use TMICT to synconize FID/VID
253 sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
260 post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now