src/mainboard/iwill/dk8_htx/romstage.c

   1 #define ASSEMBLY 1
   2
   3
   4 #define RAMINIT_SYSINFO 1
   5 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   6
   7 #define SET_NB_CFG_54 1
   8
   9 //used by raminit
  10 #define QRANK_DIMM_SUPPORT 1
  11
  12 //used by incoherent_ht
  13 //#define K8_ALLOCATE_IO_RANGE 1
  14
  15 //used by init_cpus and fidvid
  16 #define K8_SET_FIDVID 0
  17 //if we want to wait for core1 done before DQS training, set it to 0
  18 #define K8_SET_FIDVID_CORE0_ONLY 1
  19
  20 #if CONFIG_K8_REV_F_SUPPORT == 1
  21 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  22 #endif
  23
  24 #include <stdint.h>
  25 #include <string.h>
  26 #include <device/pci_def.h>
  27 #include <device/pci_ids.h>
  28 #include <arch/io.h>
  29 #include <device/pnp_def.h>
  30 #include <arch/romcc_io.h>
  31 #include <cpu/x86/lapic.h>
  32 #include "option_table.h"
  33 #include "pc80/mc146818rtc_early.c"
  34
  35 #include "pc80/serial.c"
  36 #include "arch/i386/lib/console.c"
  37 #include <cpu/amd/model_fxx_rev.h>
  38 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  39 #include "northbridge/amd/amdk8/raminit.h"
  40 #include "cpu/amd/model_fxx/apic_timer.c"
  41
  42
  43 #include "cpu/x86/lapic/boot_cpu.c"
  44 #include "northbridge/amd/amdk8/reset_test.c"
  45
  46 #include "cpu/x86/bist.h"
  47
  48 #include "lib/delay.c"
  49
  50 #include "northbridge/amd/amdk8/debug.c"
  51 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  52 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  53
  54 #include "northbridge/amd/amdk8/setup_resource_map.c"
  55
  56 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  57
  58 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  59
  60 /*
  61  * GPIO28 of 8111 will control H0_MEMRESET_L
  62  * GPIO29 of 8111 will control H1_MEMRESET_L
  63  */
  64 static void memreset_setup(void)
  65 {
  66         if (is_cpu_pre_c0()) {
  67                 /* Set the memreset low */
  68                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  69                 /* Ensure the BIOS has control of the memory lines */
  70                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  71         } else {
  72                 /* Ensure the CPU has controll of the memory lines */
  73                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  74         }
  75 }
  76
  77 static void memreset(int controllers, const struct mem_controller *ctrl)
  78 {
  79         if (is_cpu_pre_c0()) {
  80                 udelay(800);
  81                 /* Set memreset_high */
  82                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  83                 udelay(90);
  84         }
  85 }
  86
  87 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  88 {
  89 }
  90
  91 static inline int spd_read_byte(unsigned device, unsigned address)
  92 {
  93         return smbus_read_byte(device, address);
  94 }
  95
  96 #include "northbridge/amd/amdk8/amdk8.h"
  97 #include "northbridge/amd/amdk8/coherent_ht.c"
  98
  99 #include "northbridge/amd/amdk8/incoherent_ht.c"
 100
 101 #include "northbridge/amd/amdk8/raminit.c"
 102
 103 #include "lib/generic_sdram.c"
 104 #include "lib/ramtest.c"
 105
 106  /* tyan does not want the default */
 107 #include "resourcemap.c"
 108
 109 #include "cpu/amd/dualcore/dualcore.c"
 110
 111 #define DIMM0 0x50
 112 #define DIMM1 0x51
 113 #define DIMM2 0x52
 114 #define DIMM3 0x53
 115 #define DIMM4 0x54
 116 #define DIMM5 0x55
 117 #define DIMM6 0x56
 118 #define DIMM7 0x57
 119
 120
 121 #include "cpu/amd/car/copy_and_run.c"
 122 #include "cpu/amd/car/post_cache_as_ram.c"
 123
 124 #include "cpu/amd/model_fxx/init_cpus.c"
 125
 126 #include "cpu/amd/model_fxx/fidvid.c"
 127
 128 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 129 #include "northbridge/amd/amdk8/early_ht.c"
 130
 131 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 132 {
 133         static const uint16_t spd_addr[] = {
 134                         //first node
 135                         DIMM0, DIMM2, 0, 0,
 136                         DIMM1, DIMM3, 0, 0,
 137 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 138                         //second node
 139                         DIMM4, DIMM6, 0, 0,
 140                         DIMM5, DIMM7, 0, 0,
 141 #endif
 142
 143         };
 144
 145         struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 146
 147         int needs_reset; int i;
 148         unsigned bsp_apicid = 0;
 149
 150         if (!cpu_init_detectedx && boot_cpu()) {
 151                 /* Nothing special needs to be done to find bus 0 */
 152                 /* Allow the HT devices to be found */
 153
 154                 enumerate_ht_chain();
 155
 156                 /* Setup the rom access for 4M */
 157                 amd8111_enable_rom();
 158         }
 159
 160         if (bist == 0) {
 161                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 162         }
 163
 164         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 165         uart_init();
 166         console_init();
 167
 168         /* Halt if there was a built in self test failure */
 169         report_bist_failure(bist);
 170
 171         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 172
 173         setup_mb_resource_map();
 174
 175         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 176
 177 #if CONFIG_MEM_TRAIN_SEQ == 1
 178         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 179 #endif
 180         setup_coherent_ht_domain(); // routing table and start other core0
 181
 182         wait_all_core0_started();
 183 #if CONFIG_LOGICAL_CPUS==1
 184         // It is said that we should start core1 after all core0 launched
 185         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 186          * So here need to make sure last core0 is started, esp for two way system,
 187          * (there may be apic id conflicts in that case)
 188          */
 189         start_other_cores();
 190         wait_all_other_cores_started(bsp_apicid);
 191 #endif
 192
 193         /* it will set up chains and store link pair for optimization later */
 194         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 195
 196
 197 #if K8_SET_FIDVID == 1
 198
 199         {
 200                 msr_t msr;
 201                 msr=rdmsr(0xc0010042);
 202                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 203
 204         }
 205
 206         enable_fid_change();
 207
 208         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 209
 210         init_fidvid_bsp(bsp_apicid);
 211
 212         // show final fid and vid
 213         {
 214                 msr_t msr;
 215                 msr=rdmsr(0xc0010042);
 216                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 217
 218         }
 219 #endif
 220
 221         needs_reset = optimize_link_coherent_ht();
 222         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 223
 224         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 225         if (needs_reset) {
 226                 print_info("ht reset -\r\n");
 227                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 228         }
 229
 230         allow_all_aps_stop(bsp_apicid);
 231
 232         //It's the time to set ctrl in sysinfo now;
 233         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 234
 235         enable_smbus();
 236
 237 #if 0
 238         dump_smbus_registers();
 239 #endif
 240
 241         memreset_setup();
 242
 243         //do we need apci timer, tsc...., only debug need it for better output
 244         /* all ap stopped? */
 245         init_timer(); // Need to use TMICT to synconize FID/VID
 246         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 247
 248
 249 #if 0
 250         dump_pci_devices();
 251 #endif
 252
 253         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 254
 255 }