5 static void setup_mb_resource_map(void)
7 static const unsigned int register_values[] = {
8 /* Careful set limit registers before base registers which contain the enables */
9 /* DRAM Limit i Registers
18 * [ 2: 0] Destination Node ID
28 * [10: 8] Interleave select
29 * specifies the values of A[14:12] to use with interleave enable.
31 * [31:16] DRAM Limit Address i Bits 39-24
32 * This field defines the upper address bits of a 40 bit address
33 * that define the end of the DRAM region.
35 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
36 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
37 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
38 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
39 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
40 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
41 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
42 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
43 /* DRAM Base i Registers
55 * [ 1: 1] Write Enable
59 * [10: 8] Interleave Enable
61 * 001 = Interleave on A[12] (2 nodes)
63 * 011 = Interleave on A[12] and A[14] (4 nodes)
67 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
69 * [13:16] DRAM Base Address i Bits 39-24
70 * This field defines the upper address bits of a 40-bit address
71 * that define the start of the DRAM region.
73 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
74 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
75 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
76 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
77 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
78 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
79 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
80 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
82 /* Memory-Mapped I/O Limit i Registers
91 * [ 2: 0] Destination Node ID
101 * [ 5: 4] Destination Link ID
108 * 0 = CPU writes may be posted
109 * 1 = CPU writes must be non-posted
110 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
111 * This field defines the upp adddress bits of a 40-bit address that
112 * defines the end of a memory-mapped I/O region n
114 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
115 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
116 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
117 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
118 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
119 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
120 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
121 PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
123 /* Memory-Mapped I/O Base i Registers
132 * [ 0: 0] Read Enable
135 * [ 1: 1] Write Enable
136 * 0 = Writes disabled
138 * [ 2: 2] Cpu Disable
139 * 0 = Cpu can use this I/O range
140 * 1 = Cpu requests do not use this I/O range
142 * 0 = base/limit registers i are read/write
143 * 1 = base/limit registers i are read-only
145 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
146 * This field defines the upper address bits of a 40bit address
147 * that defines the start of memory-mapped I/O region i
149 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
150 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
151 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
152 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
153 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
154 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
155 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
156 PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
158 /* PCI I/O Limit i Registers
163 * [ 2: 0] Destination Node ID
173 * [ 5: 4] Destination Link ID
179 * [24:12] PCI I/O Limit Address i
180 * This field defines the end of PCI I/O region n
183 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
184 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
185 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
186 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
188 /* PCI I/O Base i Registers
193 * [ 0: 0] Read Enable
196 * [ 1: 1] Write Enable
197 * 0 = Writes Disabled
201 * 0 = VGA matches Disabled
202 * 1 = matches all address < 64K and where A[9:0] is in the
203 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
205 * 0 = ISA matches Disabled
206 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
207 * from matching agains this base/limit pair
209 * [24:12] PCI I/O Base i
210 * This field defines the start of PCI I/O region n
213 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
214 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
215 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
216 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
218 /* Config Base and Limit i Registers
223 * [ 0: 0] Read Enable
226 * [ 1: 1] Write Enable
227 * 0 = Writes Disabled
229 * [ 2: 2] Device Number Compare Enable
230 * 0 = The ranges are based on bus number
231 * 1 = The ranges are ranges of devices on bus 0
233 * [ 6: 4] Destination Node
243 * [ 9: 8] Destination Link
249 * [23:16] Bus Number Base i
250 * This field defines the lowest bus number in configuration region i
251 * [31:24] Bus Number Limit i
252 * This field defines the highest bus number in configuration regin i
254 PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link0 of CPU 0
255 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
256 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
257 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
261 max = ARRAY_SIZE(register_values);
262 setup_resource_map(register_values, max);