src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #define RAMINIT_SYSINFO 1
   5 #define CACHE_AS_RAM_ADDRESS_DEBUG 0
   6
   7 #define SET_NB_CFG_54 1
   8
   9 //used by raminit
  10 #define QRANK_DIMM_SUPPORT 1
  11
  12 //used by incoherent_ht
  13 //#define K8_SCAN_PCI_BUS 1
  14 //#define K8_ALLOCATE_IO_RANGE 1
  15
  16
  17 //used by init_cpus and fidvid
  18 #define K8_SET_FIDVID 0
  19 //if we want to wait for core1 done before DQS training, set it to 0
  20 #define K8_SET_FIDVID_CORE0_ONLY 1
  21
  22 #if K8_REV_F_SUPPORT == 1
  23 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
  24 #endif
  25
  26 #include <stdint.h>
  27 #include <device/pci_def.h>
  28 #include <device/pci_ids.h>
  29 #include <arch/io.h>
  30 #include <device/pnp_def.h>
  31 #include <arch/romcc_io.h>
  32 #include <cpu/x86/lapic.h>
  33 #include "option_table.h"
  34 #include "pc80/mc146818rtc_early.c"
  35
  36 #if USE_FAILOVER_IMAGE==0
  37 #include "pc80/serial.c"
  38 #include "arch/i386/lib/console.c"
  39 #include <cpu/amd/model_fxx_rev.h>
  40 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  41 #include "northbridge/amd/amdk8/raminit.h"
  42 #include "cpu/amd/model_fxx/apic_timer.c"
  43 #endif
  44
  45
  46
  47 #include "cpu/x86/lapic/boot_cpu.c"
  48 #include "northbridge/amd/amdk8/reset_test.c"
  49
  50 #if USE_FAILOVER_IMAGE==0
  51 #include "cpu/x86/bist.h"
  52
  53 #include "lib/delay.c"
  54
  55 #if CONFIG_USE_INIT == 0
  56         #include "lib/memcpy.c"
  57  // TODO: This doesn't compile at the moment. Fix later.
  58  // #if CONFIG_USE_PRINTK_IN_CAR == 1
  59  //        #include "lib/uart8250.c"
  60  //        #include "console/vtxprintf.c"
  61  //        #include "arch/i386/lib/printk_init.c"
  62  // #endif
  63 #endif
  64 #include "northbridge/amd/amdk8/debug.c"
  65 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  66 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  67
  68 #include "northbridge/amd/amdk8/setup_resource_map.c"
  69
  70 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  71
  72 #include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
  73
  74 /*
  75  * GPIO28 of 8111 will control H0_MEMRESET_L
  76  * GPIO29 of 8111 will control H1_MEMRESET_L
  77  */
  78 static void memreset_setup(void)
  79 {
  80         if (is_cpu_pre_c0()) {
  81                 /* Set the memreset low */
  82                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
  83                 /* Ensure the BIOS has control of the memory lines */
  84                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
  85         } else {
  86                 /* Ensure the CPU has controll of the memory lines */
  87                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
  88         }
  89 }
  90
  91 static void memreset(int controllers, const struct mem_controller *ctrl)
  92 {
  93         if (is_cpu_pre_c0()) {
  94                 udelay(800);
  95                 /* Set memreset_high */
  96                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
  97                 udelay(90);
  98         }
  99 }
 100
 101 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 102 {
 103 }
 104
 105 static inline int spd_read_byte(unsigned device, unsigned address)
 106 {
 107         return smbus_read_byte(device, address);
 108 }
 109
 110 #include "northbridge/amd/amdk8/amdk8.h"
 111 #include "northbridge/amd/amdk8/coherent_ht_car.c"
 112
 113 #include "northbridge/amd/amdk8/incoherent_ht.c"
 114
 115 #include "northbridge/amd/amdk8/raminit.c"
 116
 117 #include "sdram/generic_sdram.c"
 118 #include "ram/ramtest.c"
 119
 120  /* tyan does not want the default */
 121 #include "resourcemap.c"
 122
 123 #include "cpu/amd/dualcore/dualcore.c"
 124
 125 #define DIMM0 0x50
 126 #define DIMM1 0x51
 127 #define DIMM2 0x52
 128 #define DIMM3 0x53
 129 #define DIMM4 0x54
 130 #define DIMM5 0x55
 131 #define DIMM6 0x56
 132 #define DIMM7 0x57
 133
 134
 135 #include "cpu/amd/car/copy_and_run.c"
 136 #include "cpu/amd/car/post_cache_as_ram.c"
 137
 138 #include "cpu/amd/model_fxx/init_cpus.c"
 139
 140 #include "cpu/amd/model_fxx/fidvid.c"
 141 #endif
 142
 143 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
 144
 145 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 146 #include "northbridge/amd/amdk8/early_ht.c"
 147
 148 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 149 {
 150
 151         unsigned last_boot_normal_x = last_boot_normal();
 152
 153         /* Is this a cpu only reset? or Is this a secondary cpu? */
 154         if ((cpu_init_detectedx) || (!boot_cpu())) {
 155                 if (last_boot_normal_x) {
 156                         goto normal_image;
 157                 } else {
 158                         goto fallback_image;
 159                 }
 160         }
 161
 162         /* Nothing special needs to be done to find bus 0 */
 163         /* Allow the HT devices to be found */
 164
 165         enumerate_ht_chain();
 166
 167         /* Setup the rom access for 4M */
 168         amd8111_enable_rom();
 169
 170         /* Is this a deliberate reset by the bios */
 171         if (bios_reset_detected() && last_boot_normal_x) {
 172                 goto normal_image;
 173         }
 174         /* This is the primary cpu how should I boot? */
 175         else if (do_normal_boot()) {
 176                 goto normal_image;
 177         }
 178         else {
 179                 goto fallback_image;
 180         }
 181  normal_image:
 182         __asm__ volatile ("jmp __normal_image"
 183                 : /* outputs */
 184                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 185                 );
 186
 187  fallback_image:
 188 #if HAVE_FAILOVER_BOOT==1
 189         __asm__ volatile ("jmp __fallback_image"
 190                 : /* outputs */
 191                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 192                 )
 193 #endif
 194         ;
 195 }
 196 #endif
 197
 198 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 199
 200 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 201 {
 202 #if HAVE_FAILOVER_BOOT==1
 203     #if USE_FAILOVER_IMAGE==1
 204         failover_process(bist, cpu_init_detectedx);
 205     #else
 206         real_main(bist, cpu_init_detectedx);
 207     #endif
 208 #else
 209     #if USE_FALLBACK_IMAGE == 1
 210         failover_process(bist, cpu_init_detectedx);
 211     #endif
 212         real_main(bist, cpu_init_detectedx);
 213 #endif
 214 }
 215
 216 #if USE_FAILOVER_IMAGE==0
 217
 218 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 219 {
 220         static const uint16_t spd_addr[] = {
 221                         //first node
 222                         DIMM0, DIMM2, 0, 0,
 223                         DIMM1, DIMM3, 0, 0,
 224 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 225                         //second node
 226                         DIMM4, DIMM6, 0, 0,
 227                         DIMM5, DIMM7, 0, 0,
 228 #endif
 229
 230         };
 231
 232         struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
 233
 234         int needs_reset; int i;
 235         unsigned bsp_apicid = 0;
 236
 237         if (bist == 0) {
 238                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 239         }
 240
 241         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 242         uart_init();
 243         console_init();
 244
 245         /* Halt if there was a built in self test failure */
 246         report_bist_failure(bist);
 247
 248         print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
 249
 250         setup_mb_resource_map();
 251
 252         print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
 253
 254 #if MEM_TRAIN_SEQ == 1
 255         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
 256 #endif
 257         setup_coherent_ht_domain(); // routing table and start other core0
 258
 259         wait_all_core0_started();
 260 #if CONFIG_LOGICAL_CPUS==1
 261         // It is said that we should start core1 after all core0 launched
 262         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 263          * So here need to make sure last core0 is started, esp for two way system,
 264          * (there may be apic id conflicts in that case)
 265          */
 266         start_other_cores();
 267         wait_all_other_cores_started(bsp_apicid);
 268 #endif
 269
 270         /* it will set up chains and store link pair for optimization later */
 271         ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
 272
 273
 274 #if K8_SET_FIDVID == 1
 275
 276         {
 277                 msr_t msr;
 278                 msr=rdmsr(0xc0010042);
 279                 print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 280
 281         }
 282
 283         enable_fid_change();
 284
 285         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 286
 287         init_fidvid_bsp(bsp_apicid);
 288
 289         // show final fid and vid
 290         {
 291                 msr_t msr;
 292                 msr=rdmsr(0xc0010042);
 293                 print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
 294
 295         }
 296 #endif
 297
 298         needs_reset = optimize_link_coherent_ht();
 299         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 300
 301         // fidvid change will issue one LDTSTOP and the HT change will be effective too
 302         if (needs_reset) {
 303                 print_info("ht reset -\r\n");
 304                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 305         }
 306
 307         allow_all_aps_stop(bsp_apicid);
 308
 309         //It's the time to set ctrl in sysinfo now;
 310         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 311
 312         enable_smbus();
 313
 314 #if 0
 315         dump_smbus_registers();
 316 #endif
 317
 318         memreset_setup();
 319
 320         //do we need apci timer, tsc...., only debug need it for better output
 321         /* all ap stopped? */
 322         init_timer(); // Need to use TMICT to synconize FID/VID
 323         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 324
 325
 326 #if 0
 327         dump_pci_devices();
 328 #endif
 329
 330         post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
 331
 332 }
 333 #endif