1 include /config/failovercalculation.lb
6 ## Build the objects we have code for in this directory.
13 #needed by irq_tables and mptable and acpi_tables
25 # object acpi_tables.o
27 # if SB_HT_CHAIN_ON_BUS0
34 # if SB_HT_CHAIN_ON_BUS0
46 depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
47 action "iasl -p $(CURDIR)/dsdt_lb -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
48 action "mv dsdt_lb.hex dsdt.c"
52 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
56 depends "$(MAINBOARD)/dx/pci2.asl"
57 action "iasl -p $(CURDIR)/pci2 -tc $(MAINBOARD)/dx/pci2.asl"
58 action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
59 action "mv pci2.hex ssdt2.c"
63 depends "$(MAINBOARD)/dx/pci3.asl"
64 action "iasl -p $(CURDIR)/pci3 -tc $(MAINBOARD)/dx/pci3.asl"
65 action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
66 action "mv pci3.hex ssdt3.c"
70 depends "$(MAINBOARD)/dx/pci4.asl"
71 action "iasl -p $(CURDIR)/pci4 -tc $(MAINBOARD)/dx/pci4.asl"
72 action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
73 action "mv pci4.hex ssdt4.c"
77 depends "$(MAINBOARD)/dx/pci5.asl"
78 action "iasl -p $(CURDIR)/pci5 -tc $(MAINBOARD)/dx/pci5.asl"
79 action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
80 action "mv pci5.hex ssdt5.c"
87 # compile cache_as_ram.c to auto.o
88 makerule ./cache_as_ram_auto.o
89 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
90 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
94 #compile cache_as_ram.c to auto.inc
95 makerule ./cache_as_ram_auto.inc
96 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
97 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
98 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
99 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
104 if USE_FAILOVER_IMAGE
106 if CONFIG_AP_CODE_IN_CAR
107 makerule ./apc_auto.o
108 depends "$(MAINBOARD)/apc_auto.c option_table.h"
109 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/apc_auto.c -o $@"
111 ldscript /arch/i386/init/ldscript_apc.lb
116 ## Build our 16 bit and 32 bit coreboot entry code
119 if HAVE_FAILOVER_BOOT
120 if USE_FAILOVER_IMAGE
121 mainboardinit cpu/x86/16bit/entry16.inc
122 ldscript /cpu/x86/16bit/entry16.lds
125 if USE_FALLBACK_IMAGE
126 mainboardinit cpu/x86/16bit/entry16.inc
127 ldscript /cpu/x86/16bit/entry16.lds
131 mainboardinit cpu/x86/32bit/entry32.inc
133 ldscript /cpu/x86/32bit/entry32.lds
137 ldscript /cpu/amd/car/cache_as_ram.lds
141 ## Build our reset vector (This is where coreboot is entered)
143 if HAVE_FAILOVER_BOOT
144 if USE_FAILOVER_IMAGE
145 mainboardinit cpu/x86/16bit/reset16.inc
146 ldscript /cpu/x86/16bit/reset16.lds
148 mainboardinit cpu/x86/32bit/reset32.inc
149 ldscript /cpu/x86/32bit/reset32.lds
152 if USE_FALLBACK_IMAGE
153 mainboardinit cpu/x86/16bit/reset16.inc
154 ldscript /cpu/x86/16bit/reset16.lds
156 mainboardinit cpu/x86/32bit/reset32.inc
157 ldscript /cpu/x86/32bit/reset32.lds
162 ## Include an id string (For safe flashing)
164 mainboardinit arch/i386/lib/id.inc
165 ldscript /arch/i386/lib/id.lds
168 ## Setup Cache-As-Ram
170 mainboardinit cpu/amd/car/cache_as_ram.inc
173 ### This is the early phase of coreboot startup
174 ### Things are delicate and we test to see if we should
175 ### failover to another image.
177 if HAVE_FAILOVER_BOOT
178 if USE_FAILOVER_IMAGE
179 ldscript /arch/i386/lib/failover_failover.lds
182 if USE_FALLBACK_IMAGE
183 ldscript /arch/i386/lib/failover.lds
188 ### O.k. We aren't just an intermediary anymore!
195 initobject cache_as_ram_auto.o
197 mainboardinit ./cache_as_ram_auto.inc
201 ## Include the secondary Configuration files
205 dir /southbridge/amd/amd8132
207 chip northbridge/amd/amdk8/root_complex
208 device apic_cluster 0 on
209 chip cpu/amd/socket_940
213 device pci_domain 0 on
214 chip northbridge/amd/amdk8
215 device pci 18.0 on end
216 device pci 18.0 on end
217 device pci 18.0 on # northbridge
218 chip southbridge/amd/amd8131
219 # the on/off keyword is mandatory
220 device pci 0.0 on end
221 device pci 0.1 on end
222 device pci 1.0 on end
223 device pci 1.1 on end
225 chip southbridge/amd/amd8111
226 # this "device pci 0.0" is the parent the next one
229 device pci 0.0 on end
230 device pci 0.1 on end
231 device pci 0.2 off end
232 device pci 1.0 off end
233 #chip drivers/pci/onboard
234 # device pci 6.0 on end
235 # register "rom_address" = "0xfff80000"
239 chip superio/winbond/w83627hf
240 device pnp 2e.0 off # Floppy
245 device pnp 2e.1 off # Parallel Port
249 device pnp 2e.2 on # Com1
253 device pnp 2e.3 off # Com2
257 device pnp 2e.5 on # Keyboard
263 device pnp 2e.6 off # CIR
266 device pnp 2e.7 off # GAME_MIDI_GIPO1
271 device pnp 2e.8 on # GPIO2
277 device pnp 2e.9 off end # GPIO3
278 device pnp 2e.a off end # ACPI
279 device pnp 2e.b on # HW Monitor
285 device pci 1.1 on end
286 device pci 1.2 on end
288 chip drivers/generic/generic #dimm 0-0-0
291 chip drivers/generic/generic #dimm 0-0-1
294 chip drivers/generic/generic #dimm 0-1-0
297 chip drivers/generic/generic #dimm 0-1-1
300 chip drivers/generic/generic #dimm 1-0-0
303 chip drivers/generic/generic #dimm 1-0-1
306 chip drivers/generic/generic #dimm 1-1-0
309 chip drivers/generic/generic #dimm 1-1-1
313 device pci 1.5 off end
314 device pci 1.6 off end
315 register "ide0_enable" = "1"
316 register "ide1_enable" = "1"
318 end # device pci 18.0
320 device pci 18.1 on end
321 device pci 18.2 on end
322 device pci 18.3 on end
326 # chip drivers/generic/debug
327 # device pnp 0.0 off end # chip name
328 # device pnp 0.1 on end # pci_regs_all
329 # device pnp 0.2 off end # mem
330 # device pnp 0.3 off end # cpuid
331 # device pnp 0.4 off end # smbus_regs_all
332 # device pnp 0.5 off end # dual core msr
333 # device pnp 0.6 off end # cache size
334 # device pnp 0.7 off end # tsc