src/mainboard/island/aruma/auto.c

   1 #define ASSEMBLY 1
   2 #define ENABLE_APIC_EXT_ID 1
   3 #define APIC_ID_OFFSET 0x10
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <arch/cpu.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20 #include "cpu/x86/lapic/boot_cpu.c"
  21 #include "northbridge/amd/amdk8/reset_test.c"
  22 #include "northbridge/amd/amdk8/debug.c"
  23 #include "northbridge/amd/amdk8/incoherent_ht.c"
  24 #include "northbridge/amd/amdk8/cpu_rev.c"
  25 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  26 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  30
  31 static void hard_reset(void)
  32 {
  33         set_bios_reset();
  34         pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
  35         outb(0x0e, 0x0cf9);
  36 }
  37
  38 static void soft_reset(void)
  39 {
  40         set_bios_reset();
  41         pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
  42 }
  43
  44 /*
  45  * GPIO28 of 8111 will control H0_MEMRESET_L
  46  * GPIO29 of 8111 will control H1_MEMRESET_L
  47  */
  48 static void memreset_setup(void)
  49 {
  50         if (is_cpu_pre_c0()) {
  51                 /* Set the memreset low */
  52                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0),
  53                                 SMBUS_IO_BASE + 0xc0 + 28);
  54                 /* Ensure the BIOS has control of the memory lines */
  55                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0),
  56                                 SMBUS_IO_BASE + 0xc0 + 29);
  57         } else {
  58                 /* Ensure the CPU has controll of the memory lines */
  59                 outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0),
  60                                 SMBUS_IO_BASE + 0xc0 + 29);
  61         }
  62 }
  63
  64 static void memreset(int controllers, const struct mem_controller *ctrl)
  65 {
  66         if (is_cpu_pre_c0()) {
  67                 udelay(800);
  68                 /* Set memreset_high */
  69                 outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0),
  70                                 SMBUS_IO_BASE + 0xc0 + 28);
  71                 udelay(90);
  72         }
  73 }
  74
  75 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  76 {
  77 #define SMBUS_SWITCH1 0x71
  78 #define SMBUS_SWITCH2 0x73
  79         /* Switch 1: pca 9545, Switch 2: pca 9543 */
  80         unsigned device = (ctrl->channel0[0]) >> 8;
  81         /* Disable all outputs on SMBus switch 1 */
  82         smbus_send_byte(SMBUS_SWITCH1, 0x0);
  83         /* Select SMBus switch 2 Channel 0/1 */
  84         smbus_send_byte(SMBUS_SWITCH2, device);
  85 }
  86
  87 static inline int spd_read_byte(unsigned device, unsigned address)
  88 {
  89         return smbus_read_byte(device, address);
  90 }
  91
  92 #include "northbridge/amd/amdk8/raminit.c"
  93 #include "northbridge/amd/amdk8/coherent_ht.c"
  94 #include "sdram/generic_sdram.c"
  95 #include "resourcemap.c"
  96
  97 #define CHAN0 0x100
  98 #define CHAN1 0x200
  99
 100 #define NODE_RAM(x)                     \
 101         .node_id = 0+x,                 \
 102         .f0 = PCI_DEV(0, 0x18+x, 0),    \
 103         .f1 = PCI_DEV(0, 0x18+x, 1),    \
 104         .f2 = PCI_DEV(0, 0x18+x, 2),    \
 105         .f3 = PCI_DEV(0, 0x18+x, 3)
 106
 107 static void main(unsigned long bist)
 108 {
 109         static const struct mem_controller cpu[] = {
 110         {        NODE_RAM(0),
 111                 .channel0 = { (0xa0>>1)|CHAN0, (0xa4>>1)|CHAN0, 0, 0 },
 112                 .channel1 = { (0xa2>>1)|CHAN0, (0xa6>>1)|CHAN0, 0, 0 }
 113         },
 114         {       NODE_RAM(1),
 115                 .channel0 = { (0xa8>>1)|CHAN0, (0xac>>1)|CHAN0, 0, 0 },
 116                 .channel1 = { (0xaa>>1)|CHAN0, (0xae>>1)|CHAN0, 0, 0 }
 117         },
 118         {       NODE_RAM(2),
 119                 .channel0 = { (0xa0>>1)|CHAN1, (0xa4>>1)|CHAN1, 0, 0 },
 120                 .channel1 = { (0xa2>>1)|CHAN1, (0xa6>>1)|CHAN1, 0, 0 }
 121         },
 122         {       NODE_RAM(3),
 123                 .channel0 = { (0xa8>>1)|CHAN1, (0xac>>1)|CHAN1, 0, 0 },
 124                 .channel1 = { (0xaa>>1)|CHAN1, (0xae>>1)|CHAN1, 0, 0 }
 125         } };
 126
 127         int needs_reset;
 128
 129         if (bist == 0) {
 130                 unsigned nodeid;
 131
 132                 /* Skip this if there was a built in self test failure */
 133                 amd_early_mtrr_init();
 134                 enable_lapic();
 135                 init_timer();
 136
 137                 nodeid=lapicid() & 0xf;
 138
 139
 140 #if ENABLE_APIC_EXT_ID == 1
 141                 enable_apic_ext_id(nodeid);
 142                 if(nodeid != 0) {
 143                         /* CPU apicid is from 0x10 */
 144                         lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID)
 145                                                 | (APIC_ID_OFFSET<<24) ) );
 146                 }
 147 #endif
 148                 if (cpu_init_detected(nodeid)) {
 149                         asm volatile ("jmp __cpu_reset");
 150                 }
 151                 distinguish_cpu_resets(nodeid);
 152                 if (!boot_cpu()) {
 153                         stop_this_cpu();
 154                 }
 155         }
 156         /* Setup the console */
 157         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 158         uart_init();
 159         console_init();
 160
 161         /* Halt if there was a built in self test failure */
 162         report_bist_failure(bist);
 163
 164         setup_aruma_resource_map();
 165         needs_reset = setup_coherent_ht_domain();
 166         needs_reset=ht_setup_chains_x();
 167
 168 #if 0
 169         dump_pci_devices();
 170 #endif
 171 #if 0
 172         print_pci_devices();
 173 #endif
 174
 175 #if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0)
 176         if(read_option(CMOS_VSTART_amdk8_1GHz, CMOS_VLEN_amdk8_1GHz, 0))
 177         {
 178                 print_debug("AMDK8 allowed at 1GHz\r\n");
 179         } else {
 180                 print_debug("AMDK8 allowed at 800Hz only\r\n");
 181         }
 182         if(read_option(CMOS_VSTART_amd8131_800MHz, CMOS_VLEN_amd8131_800MHz, 0))
 183         {
 184                 print_debug("AMD8131 allowed at 800MHz\r\n");
 185         } else {
 186                 print_debug("AMD8131 allowed at 600Hz only\r\n");
 187         }
 188 #endif
 189         if (needs_reset) {
 190                 print_info("HyperT reset -\r\n");
 191                 soft_reset();
 192         }
 193
 194         enable_smbus();
 195
 196         memreset_setup();
 197         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 198
 199 #if 0
 200         /* Check the first 1M */
 201         ram_check(0x00000000, 0x000100000);
 202 #endif
 203 }