4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
9 uses HARD_RESET_FUNCTION
11 uses HAVE_OPTION_TABLE
20 uses ROM_SECTION_OFFSET
21 uses CONFIG_ROM_STREAM
22 uses CONFIG_ROM_STREAM_START
30 uses LB_CKS_RANGE_START
34 uses MAINBOARD_PART_NUMBER
36 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses LINUXBIOS_EXTRA_VERSION
46 uses DEFAULT_CONSOLE_LOGLEVEL
47 uses MAXIMUM_CONSOLE_LOGLEVEL
48 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
49 uses CONFIG_CONSOLE_SERIAL8250
52 uses CONFIG_CONSOLE_VGA
53 uses CONFIG_PCI_ROM_RUN
60 ## ROM_SIZE is the size of boot ROM that this board will use.
62 default ROM_SIZE=524288
65 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
67 #default FALLBACK_SIZE=131072
69 default FALLBACK_SIZE=0x40000
72 ## Build code for the fallback boot
74 default HAVE_FALLBACK_BOOT=1
77 ## incoherent_ht.c does all the work. we don't want hard reset.
79 default HAVE_HARD_RESET=0
82 ## Funky hard reset implementation
84 default HARD_RESET_BUS=1
85 default HARD_RESET_DEVICE=4
86 default HARD_RESET_FUNCTION=0
89 ## Build code to export a programmable irq routing table
91 default HAVE_PIRQ_TABLE=1
92 default IRQ_SLOT_COUNT=23
95 ## Build code to export an x86 MP table
96 ## Useful for specifying IRQ routing values
98 default HAVE_MP_TABLE=1
99 default HAVE_ACPI_TABLES=1
102 ## Build code to export a CMOS option table
104 default HAVE_OPTION_TABLE=1
107 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
109 default LB_CKS_RANGE_START=49
110 default LB_CKS_RANGE_END=122
111 default LB_CKS_LOC=123
114 ## Build code for SMP support
115 ## Only worry about 2 micro processors
118 default CONFIG_MAX_CPUS=4
119 #default ALLOW_HT_OVERCLOCKING=1
122 ## Build code to setup a generic IOAPIC
124 default CONFIG_IOAPIC=1
127 ## Clean up the motherboard id strings
129 default MAINBOARD_PART_NUMBER="ARUMA"
130 default MAINBOARD_VENDOR="ISLAND"
131 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
132 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x36c0
136 ### LinuxBIOS layout values
139 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
140 default ROM_IMAGE_SIZE = 65536
143 ## Use a small 8K stack
145 default STACK_SIZE=0x2000
150 default HEAP_SIZE=0x8000
153 ## Only use the option table in a normal image
155 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
158 ## LinuxBIOS C code runs at this location in RAM
160 default _RAMBASE=0x00004000
163 ## Load the payload from the ROM
165 default CONFIG_ROM_STREAM = 1
168 ### Defaults of options that you may want to override in the target config file
172 ## The default compiler
174 default CC="$(CROSS_COMPILE)gcc -m32"
178 ## The Serial Console
181 # To Enable the Serial Console
182 default CONFIG_CONSOLE_SERIAL8250=1
184 ## Select the serial console baud rate
185 #default TTYS0_BAUD=115200
186 #default TTYS0_BAUD=57600
187 #default TTYS0_BAUD=38400
188 default TTYS0_BAUD=19200
189 #default TTYS0_BAUD=9600
190 #default TTYS0_BAUD=4800
191 #default TTYS0_BAUD=2400
192 #default TTYS0_BAUD=1200
194 # Select the serial console base port
195 default TTYS0_BASE=0x3f8
197 # Select the serial protocol
198 # This defaults to 8 data bits, 1 stop bit, and no parity
199 default TTYS0_LCS=0x3
202 ### Select the linuxBIOS loglevel
204 ## EMERG 1 system is unusable
205 ## ALERT 2 action must be taken immediately
206 ## CRIT 3 critical conditions
207 ## ERR 4 error conditions
208 ## WARNING 5 warning conditions
209 ## NOTICE 6 normal but significant condition
210 ## INFO 7 informational
211 ## DEBUG 8 debug-level messages
212 ## SPEW 9 Way too many details
214 ## Request this level of debugging output
215 default DEFAULT_CONSOLE_LOGLEVEL=8
216 ## At a maximum only compile in this level of debugging
217 default MAXIMUM_CONSOLE_LOGLEVEL=8
220 ## Select power on after power fail setting
221 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
224 default CONFIG_CONSOLE_VGA=1
225 default CONFIG_PCI_ROM_RUN=1