src/mainboard/intel/xe7501devkit/romstage.c

   1 #include <stdint.h>
   2 #include <device/pci_def.h>
   3 #include <arch/io.h>
   4 #include <device/pnp_def.h>
   5 #include <arch/romcc_io.h>
   6 #include <cpu/x86/lapic.h>
   7 #include <arch/cpu.h>
   8 #include <stdlib.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "console/console.c"
  13 #include "lib/ramtest.c"
  14 #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
  15 #include "northbridge/intel/e7501/raminit.h"
  16 #include "cpu/x86/lapic/boot_cpu.c"
  17 #include "northbridge/intel/e7501/debug.c"
  18 #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
  19 #include "cpu/x86/mtrr/earlymtrr.c"
  20 #include "cpu/x86/bist.h"
  21
  22 #define SUPERIO_PORT    0x2e
  23 #define SERIAL_DEV              PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)
  24
  25 static void hard_reset(void)
  26 {
  27         outb(0x0e, 0x0cf9);
  28 }
  29
  30 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  31 {
  32         /* nothing to do */
  33 }
  34
  35 static inline int spd_read_byte(unsigned device, unsigned address)
  36 {
  37         return smbus_read_byte(device, address);
  38 }
  39
  40 #include "northbridge/intel/e7501/raminit.c"
  41 #include "northbridge/intel/e7501/reset_test.c"
  42 #include "lib/generic_sdram.c"
  43
  44 // This function MUST appear last (ROMCC limitation)
  45 static void main(unsigned long bist)
  46 {
  47         static const struct mem_controller memctrl[] = {
  48                 {
  49                         .d0 = PCI_DEV(0, 0, 0),
  50                         .d0f1 = PCI_DEV(0, 0, 1),
  51                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
  52                         .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
  53                 },
  54         };
  55
  56         if (bist == 0)
  57         {
  58                 // Skip this if there was a built in self test failure
  59
  60                 early_mtrr_init();
  61         enable_lapic();
  62     }
  63
  64         // Get the serial port running and print a welcome banner
  65
  66     lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  67     uart_init();
  68     console_init();
  69
  70     // Halt if there was a built in self test failure
  71         report_bist_failure(bist);
  72
  73 //      print_pci_devices();
  74
  75         // If this is a warm boot, some initialization can be skipped
  76
  77         if (!bios_reset_detected())
  78         {
  79                 enable_smbus();
  80 //      dump_spd_registers(&memctrl[0]);
  81 //      dump_smbus_registers();
  82
  83 //              memreset_setup();               No-op for this chipset
  84                 sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
  85         }
  86
  87         // NOTE: ROMCC dies with an internal compiler error
  88         //               if the following line is removed.
  89         print_debug("SDRAM is up.\r\n");
  90 }
  91