src/mainboard/intel/xe7501devkit/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include <arch/cpu.h>
  11 #include <stdlib.h>
  12 #include "option_table.h"
  13 #include "pc80/mc146818rtc_early.c"
  14 #include "pc80/serial.c"
  15 #include "arch/i386/lib/console.c"
  16 #include "lib/ramtest.c"
  17 #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
  18 #include "northbridge/intel/e7501/raminit.h"
  19 #include "cpu/x86/lapic/boot_cpu.c"
  20 #include "northbridge/intel/e7501/debug.c"
  21 #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
  22 #include "cpu/x86/mtrr/earlymtrr.c"
  23 #include "cpu/x86/bist.h"
  24
  25 #define SUPERIO_PORT    0x2e
  26 #define SERIAL_DEV              PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)
  27
  28 static void hard_reset(void)
  29 {
  30         outb(0x0e, 0x0cf9);
  31 }
  32
  33 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  34 {
  35         /* nothing to do */
  36 }
  37
  38 static inline int spd_read_byte(unsigned device, unsigned address)
  39 {
  40         return smbus_read_byte(device, address);
  41 }
  42
  43 #include "northbridge/intel/e7501/raminit.c"
  44 #include "northbridge/intel/e7501/reset_test.c"
  45 #include "lib/generic_sdram.c"
  46
  47
  48 // This function MUST appear last (ROMCC limitation)
  49 static void main(unsigned long bist)
  50 {
  51         static const struct mem_controller memctrl[] = {
  52                 {
  53                         .d0 = PCI_DEV(0, 0, 0),
  54                         .d0f1 = PCI_DEV(0, 0, 1),
  55                         .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
  56                         .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
  57                 },
  58         };
  59
  60         if (bist == 0)
  61         {
  62                 // Skip this if there was a built in self test failure
  63
  64                 early_mtrr_init();
  65         enable_lapic();
  66     }
  67
  68         // Get the serial port running and print a welcome banner
  69
  70     lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  71     uart_init();
  72     console_init();
  73
  74     // Halt if there was a built in self test failure
  75         report_bist_failure(bist);
  76
  77 //      print_pci_devices();
  78
  79         // If this is a warm boot, some initialization can be skipped
  80
  81         if (!bios_reset_detected())
  82         {
  83                 enable_smbus();
  84 //      dump_spd_registers(&memctrl[0]);
  85 //      dump_smbus_registers();
  86
  87 //              memreset_setup();               No-op for this chipset
  88                 sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
  89         }
  90
  91         // NOTE: ROMCC dies with an internal compiler error
  92         //               if the following line is removed.
  93         print_debug("SDRAM is up.\r\n");
  94 }